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AD8389ACPZ Datasheet(PDF) 8 Page - Analog Devices |
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AD8389ACPZ Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page AD8389 Rev. 0 | Page 8 of 12 The phase detector compares the delayed DX and MONITxI reference inputs and automatically adjusts the variable delay (t5), maintaining the constant delay (t7) between the active edges of DX and MONITxI. Five matched delay lines maintain the phase relationship between DXxO, CLXxO, and ENBX(1–4)xO. When the loop is locked, t7 = t5 + tEXT, where tEXT is the total delay through the level shifter and the LCD. The external delay of a typical system is the sum of the level shifter delay (20 ns typical) and the LCD delay, (typically in the range of 20 ns to 120 ns). At a 75 MHz operating clock frequency, the maximum expected total delay of 140 ns is equal to 10.5 clock cycles, requiring COMPEDGE = 1, SLOW = 0 for systems using negative active edge for DX. MONITRI CLX ENBX1 ENBX2 ENBX3 ENBX4 CONSTANT CLK DX DXO MONITI CLXO ENBX1O ENBX2O ENBX3O ENBX4O Figure 7. Typical Input Waveforms at the AD8389 and at the LCD. COMPEDGE = HIGH. |
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