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AD9510 Datasheet(PDF) 4 Page - Analog Devices

No. de Pieza. AD9510
Descripción  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
Descarga  60 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD9510 Datasheet(HTML) 4 Page - Analog Devices

 
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AD9510
Rev. A | Page 4 of 60
SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUTS (REFIN)
Input Frequency
0
250
MHz
Input Sensitivity
150
mV p-p
Self-Bias Voltage, REFIN
1.45
1.60
1.75
V
Self-bias voltage of REFIN1.
Self-Bias Voltage, REFINB
1.40
1.50
1.60
V
Self-bias voltage of REFINB1.
Input Resistance, REFIN
4.0
4.9
5.8
Self-biased1.
Input Resistance, REFINB
4.5
5.4
6.3
Self-biased1.
Input Capacitance
2
pF
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
100
MHz
Antibacklash pulse width 0Dh<1:0> = 00b.
PFD Input Frequency
100
MHz
Antibacklash pulse width 0Dh<1:0> = 01b.
PFD Input Frequency
45
MHz
Antibacklash pulse width 0Dh<1:0> = 10b.
Antibacklash Pulse Width
1.3
ns
0Dh<1:0> = 00b (this is the default setting).
Antibacklash Pulse Width
2.9
ns
0Dh<1:0> = 01b.
Antibacklash Pulse Width
6.0
ns
0Dh<1:0> = 10b.
CHARGE PUMP (CP)
ICP Sink/Source
Programmable.
High Value
4.8
mA
Low Value
0.60
mA
With CPRSET = 5.1 kΩ.
Absolute Accuracy
2.5
%
VCP = VCPs/2.
CPRSET Range
2.7/10
ICP Three-State Leakage
1
nA
Sink-and-Source Current Matching
2
%
0.5 < VCP < VCPs − 0.5 V.
ICP vs. VCP
1.5
%
0.5 < VCP < VCPs − 0.5 V.
ICP vs. Temperature
2
%
VCP = VCPs/2 V.
RF CHARACTERISTICS (CLK2)2
Input Frequency
1.6
GHz
Frequencies > 1200 MHz (LVPECL) or 800 MHz
(LVDS) require a minimum divide-by-2 (see the
Distribution Section).
Input Sensitivity
150
mV p-p
Input Common-Mode Voltage, VCM
1.5
1.6
1.7
V
Self-biased; enables ac coupling.
Input Common-Mode Range, VCMR
1.3
1.8
V
With 200 mV p-p signal applied.
Input Sensitivity, Single-Ended
150
mV p-p
CLK2 ac-coupled; CLK2B capacitively
bypassed to RF ground.
Input Resistance
4.0
4.8
5.6
Self-biased.
Input Capacitance
2
pF
CLK2 VS. REFIN DELAY
500
ps
Difference at PFD.
PRESCALER (PART OF N DIVIDER)
See the VCO/VCXO Feedback Divider—N (P, A, B)
section.
Prescaler Input Frequency
P = 2 DM (2/3)
600
MHz
P = 4 DM (4/5)
1000
MHz
P = 8 DM (8/9)
1600
MHz
P = 16 DM (16/17)
1600
MHz
P = 32 DM (32/33)
1600
MHz
CLK2 Input Frequency for PLL
300
MHz
A, B counter input frequency.


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