AD9510 datasheet(39/60 Pages) AD

No. de pieza	AD9510

Descripción Electrónicos	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Download	60 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

Logo

39 / 60 page

AD9510

Rev. A | Page 39 of 60

Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6

DIV = 18

Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,

11, 12, 13, 14, 15, 16, 17

Phase offsets may be related to degrees by calculating the phase

step for a particular divide ratio:

Phase Step = 360°/(Divide Ratio) = 360°/DIV

Using some of the same examples,

DIV = 4

Phase Step = 360°/4 = 90°

Unique Phase Offsets in Degrees Are Phase = 0°, 90°,

180°, 270°

DIV = 7

Phase Step = 360°/7 = 51.43°

Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°,

102.86°, 154.29°, 205.71°, 257.15°, 308.57°

DELAY BLOCK

OUT5 and OUT6 (LVDS/CMOS) include an analog delay

element that can be programmed (Register 34h to Register 3Ah)

to give variable time delays (Δt) in the clock signal passing

through that output.

ΔT

FINE DELAY ADJUST

(32 STEPS)

FULL-SCALE: 1ns TO 10ns

OUT5

OUT6 ONLY

CLOCK INPUT

÷N

∅SELECT

LVDS

CMOS

OUTPUT

DRIVER

Figure 40. Analog Delay (OUT5 andOUT6)

The amount of delay that can be used is determined by the

frequency of the clock being delayed. The amount of delay can

approach one-half cycle of the clock period. For example, for a

10 MHz clock, the delay can extend to the full 10 ns maximum

of which the delay element is capable. However, for a 100 MHz

clock (with 50% duty cycle), the maximum delay is less than

5 ns (or half of the period).

OUT5 and OUT6 allow a full-scale delay in the range 1 ns to

10 ns. The full-scale delay is selected by choosing a combination

of ramp current and the number of capacitors by writing the

appropriate values into Register 35h and Register 39h. There are

32 fine delay settings for each full scale, set by Register 36h and

Register 3Ah.

This path adds some jitter greater than that specified for the

nondelay outputs. This means that the delay function should be

used primarily for clocking digital chips, such as FPGA, ASIC,

DUC, and DDC, rather than for data converters. The jitter is

higher for long full scales (~10 ns). This is because the delay

block uses a ramp and trip points to create the variable delay. A

longer ramp means more noise might be introduced.

Calculating the Delay

The following values and equations are used to calculate the

delay of the delay block.

Value of Ramp Current Control Bits (Register 35h or Register 39h

<2:0>) = Iramp_bits

IRAMP (μA) = 200 × (Iramp_bits + 1)

No. of Caps = No. of 0s + 1 in Ramp Control Capacitor

(Register 35h or Register 39h <5:3>), that is, 101 = 1 + 1 = 2; 110

= 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1)

Delay_Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286

()

6

1

10

1600

0.34

ns

4

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

+

×

−

+

=

−

RAMP

I

Caps

of

No.

I

Offset

Delay_Full_Scale (ns) = Delay_Range + Offset

Fine_Adj = Value of Delay Fine Adjust (Register 36h or

Register 3Ah <5:1>), that is, 11111 = 31

Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31)

OUTPUTS

The AD9510 offers three different output level choices:

LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL only.

OUT4 to OUT7 can be selected as either LVDS or CMOS. Each

output can be enabled or turned off as needed to save power.

The simplified equivalent circuit of the LVPECL outputs is

shown in Figure 41.

3.3V

OUT

OUTB

GND

Figure 41. LVPECL Output Simplified Equivalent Circuit

Número de pieza similar - AD9510

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Analog Devices	AD9510	1Mb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
	AD9510	886Kb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs REV. B
	AD9510	1Mb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

More results

Descripción similar - AD9510

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Analog Devices	AD9510	1Mb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
	AD9510	886Kb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs REV. B
	AD9511	1Mb / 60P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs REV. A
	AD9511	1Mb / 60P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs REV. A
	AD9512BCPZ	967Kb / 48P	1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs REV. A
	AD9514	633Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs REV. 0
	AD9515	656Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs REV. 0
	AD9514	634Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs REV. 0
	AD9515	407Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs Rev. B
	AD9515	469Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs REV. A

More results

AD9510 Datasheet(PDF) 39 Page - Analog Devices

AD9510 Datasheet(HTML) 39 Page - Analog Devices

Número de pieza similar - AD9510

Descripción similar - AD9510

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Descarga

Enlace URL