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AD9515BCPZ Datasheet(PDF) 10 Page - Analog Devices |
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AD9515BCPZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 28 page AD9515 Rev. 0 | Page 10 of 28 POWER Table 7. Parameter Min Typ Max Unit Test Conditions/Comments POWER-ON SYNCHRONIZATION1 35 ms See the Power-On SYNC section. VS Transit Time from 2.2 V to 3.1 V POWER DISSIPATION 215 285 380 mW Both outputs on. LVPECL (divide = 2), LVDS (divide = 2). No clock. Does not include power dissipated in external resistors. 300 370 465 mW Both outputs on. LVPECL (divide = 2), CMOS (divide = 2); at 62.5 MHz out (5 pF load). 330 405 510 mW Both outputs on. LVPECL, CMOS (divide = 2); at 125 MHz out (5 pF load). POWER DELTA Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock. LVPECL Output 65 90 125 mW For each output. No clock. LVDS Output 20 50 85 mW No clock. CMOS Output (Static) 30 40 50 mW No clock. CMOS Output (@ 62.5 MHz) 80 110 140 mW Single-ended. At 62.5 MHz out with 5 pF load. CMOS Output (@ 125 MHz) 110 150 190 mW Single-ended. At 125 MHz out with 5 pF load. Delay Block 30 45 65 mW Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz. 1 This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized. |
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