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AT91SC512384RCT Datasheet(Hoja de datos) 3 Page - ATMEL Corporation

No. de Pieza. AT91SC512384RCT
Descripción  32-bit Secure Microcontrollers
Descarga  5 Pages
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Fabricante  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
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AT91SC512384RCT
6525AS–SMIC–16Jan06
Architectural Overview
The SC100 is a 3 stage pipeline, 32-bit RISC processor. It uses a Von Neumann Load/store architecture, this architecture
is characterized by a single data and address bus for instruction data. The SC100 processor employs a unique architectural
strategy known as Thumb®, a super reduced instruction set that is ideally suited for high volume applications with memory
restrictions, and applications where code density is an important factor. Essentially, the SC100 processor has two
instruction sets:
The standard ARM instruction set using 32-bit instructions and offering maximum performance
The Thumb instruction set using 16-bit instructions and offering maximum code density
Both instruction sets operate on 8-bit, 16-bit and 32-bit data types.
The Thumb’s 16-bit instruction length allows it to achieve almost twice the density of standard ARM code, whilst retaining
most of the ARM performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because
the 16-bit Thumb instructions operate on the same 32-bit register set as the 32-bit ARM instruction set. Thumb code can be
up to 35% smaller than the equivalent ARM code, whilst providing 160% of the performance of an equivalent ARM
processor connected to a 16-bit memory system.
Figure 1 shows the block diagram of the AT91SC512384RCT device.
USB XOUT
USB XOUT
SS/IO4
SPI Slave Select/Flash Interface IO4
WP
Flash Interface (Write Protect)
SCK/IO5
SPI Clock/Flash Interface IO5
MOSI/IO6
SPI Master Output-Slave Input/Flash Interface
IO6
MISO/IO7
SPI Master Output-Slave Input/Flash Interface
IO7




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