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KM62U256D Datasheet(PDF) 2 Page - Samsung semiconductor

No. de Pieza. KM62U256D
Descripción  32Kx8 bit Low Power and Low Voltage CMOS Static RAM
Descarga  9 Pages
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Fabricante  SAMSUNG [Samsung semiconductor]
Página de inicio  http://www.samsung.com/Products/Semiconductor
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KM62U256D Datasheet(HTML) 2 Page - Samsung semiconductor

   
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KM62V256D, KM62U256D Family
CMOS SRAM
Revision 1.0
November 1997
2
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The KM62V256D and KM62U256D families are fabricated
by SAMSUNG
′s advanced CMOS process technology. The
families support various operating temperature range and
have various package types for user flexibility of system
design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
FEATURES
• Process Technology : TFT
• Organization : 32Kx8
• Power Supply Voltage
KM62V256D family : 2.7~3.3V
KM62U256D family : 3.0~3.6V
• Low Data Retention Voltage : 2V(Min)
• Three state output and TTL Compatible
• Package Type : 28-SOP-450
28-TSOP1-0813.4F/R
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
2. KM62V256D Family support SOP package without 100ns speed bin.
Product
Family
Operating
Temperature
VCC Range
Speed
(ns)
Power Dissipation
PKG Type
Standby
(ISB1, Max)
Operating
(Icc2)
KM62V256DL-L
Commercial(0~70
°C)
3.0V ~3.6V
701)/100
5
µA
35mA
28-SOP2)
28-TSOP1-F/R
KM62U256DL-L
2.7V ~ 3.3V
701)/85/100
KM62V256DLE-L
Extended(-25~85
°C)
3.0V ~3.6V
701)/100
KM62U256DLE-L
2.7V ~ 3.3V
701)/85/100
KM62V256DLI-L
Industrial(-40~85
°C)
3.0V ~3.6V
701)/100
KM62U256DLI-L
2.7V ~ 3.3V
701)/85/100
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
PIN DESCRIPTION
Pin Name
Function
Pin Name
Function
CS
Chip Select Input
I/O1~I/O8
Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
A0~A14
Address Inputs
NC
No connect
FUNCTIONAL BLOCK DIAGRAM
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
28-SOP
15
16
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A11
A9
A8
A13
WE
VCC
A3
A14
A12
A7
A6
A5
A4
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
28-TSOP
Type1 - Forward
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
28
25
24
23
22
21
20
19
18
17
16
15
OE
28-TSOP
A11
A9
A8
A13
WE
VCC
A3
A14
A12
A7
A6
A5
A4
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
28
25
24
23
22
21
20
19
18
17
16
15
OE
Type1 - Reverse
Precharge circuit.
Memory array
256 rows
128
×8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A10 A3
A0
A1
A2
A11
A9
A13
A8
A12
A14
A4
A5
A7
CS
WE
I/O1
Data
cont
Data
cont
OE
I/O8
A6
Control
logic


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