Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼

Delete All


Preview PDF Download HTML

AM42DL6404G Datasheet(PDF) 2 Page - SPANSION

No. de Pieza. AM42DL6404G
Descripción  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Descarga  61 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Página de inicio

AM42DL6404G Datasheet(HTML) 2 Page - SPANSION

Zoom Inzoom in Zoom Outzoom out
 2 / 61 page
background image
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 26092
Rev: A Amendment/+1
Issue Date: March 20, 2002
Refer to AMD’s Website ( for the latest information.
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM
MCP Features
s Power supply voltage of 2.7 to 3.3 volt
s High performance
— Access time as fast as 70 ns
s Package
— 73-Ball FBGA
s Operating Temperature
— –40°C to +85°C
Flash Memory Features
s Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
s Flexible Bank
 architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
s Manufactured on 0.17 µm process technology
s SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
— Customer lockable: Sector is one-time programmable. Once
sector is locked, data cannot be changed.
s Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
s Boot sectors
— Top and bottom boot sectors in the same device
s Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
s High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
s Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
s Minimum 1 million write cycles guaranteed per sector
s 20 year data retention at 125
— Reliable operation for the life of the system
s Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
s Supports Common Flash Memory Interface (CFI)
s Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
s Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
s Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
s Any combination of sectors can be erased
s Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
s Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
s WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
s Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
SRAM Features
s Power dissipation
— Operating: 22 mA maximum
— Standby: 10 µA maximum
s CE1s# and CE2s Chip Select
s Power down features using CE1s# and CE2s
s Data retention supply voltage: 1.5 to 3.3 volt
s Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61 

Datasheet Download

Enlace URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©

Mirror Sites
English :  |   English :  |   Chinese :  |   German :  |   Japanese :
Russian :  |   Korean :  |   Spanish :  |   French :  |   Italian :
Portuguese :  |   Polish :  |   Vietnamese :