C9812 datasheet(11/18 Pages) CYPRESS

No. de pieza	C9812

Descripción Electrónicos	Low EMI Clock Generator for Intel 810E Chipset Systems

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Fabricante Electrónico	CYPRESS [Cypress Semiconductor]

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Low EMI Clock Generator for Intel

 810E Chipset Systems

Cypress Semiconductor Corporation

525 Los Coches St.

Document#: 38-07053 Rev. **

05/03/01

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

Page 11 of 18

http://www.cypress.com

APPROVED PRODUCT

C9812

AC Parameters

133 MHz Host

100 MHz Host

Symbol

Parameter

Min

Max

Min

Max

Units

Notes

TPeriod

CPU(0:1) period

7.5

8.0

10.0

10.5

nS

5, 6, 8

THIGH

CPU(0:1) high time

1.87

-

3.0

-

nS

6,10

TLOW

CPU(0:1) low time

1.67

-

2.8

-

nS

6, 11

Tr / Tf

CPU(0:1) rise and fall times

0.4

1.6

0.4

1.6

nS

6, 7

TSKEW

CPU0 to CPU1 Skew time

-

175

-

175

pS

6, 8, 9

TCCJ

CPU(0:1) Cycle to Cycle Jitter

-

250

-

250

pS

6, 8, 9

TPeriod

APIC(0:1) period

60.0

-

60.0

-

nS

5, 6, 8

THIGH

APIC(0:1) high time

25.5

-

25.5

-

nS

6,10

TLOW

APIC(0:1) low time

25.3

-

25.3

N/S

nS

6, 11

Tr / Tf

APIC(0:1) rise and fall times

0.4

1.6

0.4

1.6

nS

6, 7

TCCJ

APIC(0:1) Cycle to Cycle Jitter

-

500

-

500

pS

6, 8, 9

TPeriod

3V66-(0:1) period

15.0

16.0

15.0

16.0

nS

5, 6, 8

THIGH

3V66-(0:1) high time

5.25

-

5.25

-

nS

6,10

TLOW

3V66-(0:1) low time

5.05

-

5.05

-

nS

6, 11

Tr / Tf

3V66-(0:1) rise and fall times

0.4

1.6

0.4

1.6

nS

6, 7

TSKEW

3V66-0 to 3V66-1 Skew time

-

250

-

250

pS

6, 8, 9

TCCJ

3V66-(0:1) Cycle to Cycle Jitter

-

500

-

500

pS

6, 8, 9

TPeriod

PCI(0:7) period

30.0

-

30.0

-

nS

5, 6, 8

THIGH

PCI(0:7) period

12.0

-

12.0

-

nS

6,10

TLOW

PCI(0:7) low time

12.0

-

12.0

-

nS

6, 11

Tr / Tf

PCI(0:7) rise and fall times

0.5

2.0

0.5

2.0

nS

6, 7

TSKEW

(Any PCI clock) to (Any PCI clock)

Skew time

-

500

-

500

pS

6, 8, 9

TCCJ

PCI(0:7) Cycle to Cycle Jitter

-

500

-

500

pS

6, 8, 9

TPeriod

48MHz period ( conforms to

+167ppm max)

20.8299

20.8333

20.8299

20.8333

nS

5, 6, 8

Tr / Tf

48MHz rise and fall times

1.0

4.0

1.0

4.0

nS

6, 7

TCCJ

48MHz Cycle to Cycle Jitter

-

500

-

500

pS

6, 8, 9

TPeriod

REF period

69.8413

71.0

69.8413

71.0

nS

5, 6, 8

Tr / Tf

REF rise and fall times

1.0

4.0

1.0

4.0

nS

6, 7

TCCJ

REF Cycle to Cycle Jitter

-

1000

-

1000

pS

6, 8

tpZL, tpZH

Output enable delay (all outputs)

1.0

10.0

1.0

10.0

nS

13

tpLZ, tpZH

Output disable delay (all outputs)

1.0

10.0

1.0

10.0

nS

13

tstable

All clock Stabilization from power-up

3

mS

12

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