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FS6261-01 Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

No. de Pieza. FS6261-01
Descripción  Motherboard Clock Generator IC
Descarga  17 Pages
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Fabricante  ETC1 [List of Unclassifed Manufacturers]
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FS6261-01 Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

 
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  X T
January 2000
1.31.00
2
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,62
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U = Input with Internal Pull-Up; DI
D = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
TYPE
NAME
DESCRIPTION
53, 54, 55
DO
APIC_0:2
Three low-skew (<250ps @ 1.25V) 2.5V 16.67MHz clock outputs for APIC bus timing. APIC
clocks are synchronous with CPU clocks but lag the CPU clocks by 1.5 to 4ns.
30
DO
CK48
One 3.3V 48MHz clock output for Universal Serial Bus (USB) timing
21, 22, 25, 26
DO
CK66_0:3
Four 3.3V 66MHz AGP clock outputs. CK66 clocks are synchronous with CPU clocks but lag the
CPU clocks by 0 to 1.5ns.
41, 42, 45, 46
DO
CPU_0:3
Four low-skew 2.5V 133/100MHz CPU clock outputs for host frequencies
49, 50
DO
CPU/2_0:1
Two low-skew 2.5V clock outputs at half the CPU clock frequencies (66/50MHz)
36
DI
U
CPU_STOP#
CPU_0:3 and CK66_0:3 clock output enable. Asynchronous, active-low disable stops all CPU
and CK66 clocks in the low state.
9, 11, 12, 14,
15, 17, 18
DO
PCI_1:7
Seven 3.3V PCI clock outputs. PCI clocks are synchronous with CPU clocks but lag the CK66
clocks by 1.5 to 4ns.
8
DO
PCI_F
One free-running 3.3V PCI clock output
37
DI
U
PCI_STOP#
PCI_1:7 clock output enable. Asynchronous, active-low disable stops all PCI clocks in the low
state.
35
DI
U
PWR_DWN#
Asynchronous active-low power-down signal shuts down oscillator, all PLLs, puts all clocks in
low state. Clock re-enable latency of
≤ 3ms.
2, 3
DO
REF_0:1
Two buffered outputs of the 14.318MHz reference clock
32, 33
DI
U
SEL_0:1
Two frequency select inputs (see Table 4)
28
DI
SEL_133/100#
Selects 133MHz or 100MHz CPU frequency (pull-up/pull-down
must be provided externally)
34
DI
U
SS_EN#
Spread spectrum enable. Active-low enable turns on the spread spectrum feature; a logic-high
turns off the spread spectrum modulation.
39
P
VDD
3.3V ± 10%
31
P
VDD_48
Power supply for 3.3V CK48 clock output
23, 27
P
VDD_66
Power supply for 3.3V CK66_0:3 clock outputs
56
P
VDD_A
Power supply for 2.5V APIC_0:2 clock outputs
43, 47
P
VDD_C
Power supply for 2.5V CPU_0:3 clock outputs
51
P
VDD_C2
Power supply for 2.5V CPU/2_0:1 clock outputs
10, 16
P
VDD_P
Power supply for 3.3V PCI_1:7 and PCI_F clock outputs
4
P
VDD_R
Power supply for 3.3V REF_0:1 clock outputs
38
P
VSS
Ground
29
P
VSS_48
Ground for CK48 clock outputs
20, 24
P
VSS_66
Ground for CK66_0:3 clock outputs
52
P
VSS_A
Ground for APIC_0:2 clock outputs
40, 44
P
VSS_C
Ground for CPU_0:3 clock outputs
48
P
VSS_C2
Ground for CPU/2_0:1 clock outputs
7, 13, 19
P
VSS_P
Ground for PCI_1:7 and PCI_F clock outputs
1
P
VSS_R
Ground for REF_0:1 clock outputs
5
AI
XIN
14.318MHz crystal oscillator input. XIN can be driven by an external frequency source.
6
AO
XOUT
14.318MHz crystal oscillator output


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