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MK1491-14 Datasheet(PDF) 3 Page - Integrated Circuit Systems

No. de Pieza. MK1491-14
Descripción  OPTi ACPI Firestar Clock Source
Descarga  4 Pages
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Fabricante  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
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MK1491-14 Datasheet(HTML) 3 Page - Integrated Circuit Systems

   
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MK1491-14
OPTi ACPI Firestar Clock Source
MDS 1491-14 B
3
Revision 061801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126 • (408)295-9800tel • www.icst.com
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3V or 2.5V unless noted)
DC CHARACTERISTICS (VDD = 3.3V or 2.5V unless noted)
Operating Voltage
VDD
3.3
3.6
V
Operating Voltage
2.5/3.3
VDD
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-8mA
2.4
V
Output Low Voltage, VOL
IOL=8mA
0.4
V
Output High Voltage, VOH
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, 66.6MHz
48
mA
Power Down mode Supply Current
3
µΑ
Short Circuit Current
Each output
±50
mA
Short Circuit Current
±25
mA
Input Capacitance
7
pF
AC CHARACTERISTICS (VDD = 3.3V or 2.5V unless noted)
AC CHARACTERISTICS (VDD = 3.3V or 2.5V unless noted)
Input Frequency
14.31818
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
HOST Output Clock Rise Time
2.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
HOST Output Clock Fall Time
2.5
ns
Output Clock Duty Cycle, all MHz clocks
At 1.5V
45
49 to 51
55
%
HOST1-4 Output to Output Skew
Rising edges at 1.5V
250
ps
Skew of HOST 5,7 with respect to HOST 1-4
With proper HSKEW setting
750
ps
PCI Output to Output Skew
Rising edges at 1.5V
500
ps
Lead of EHOST6 outputs with respect to PCI
Rising edges at 1.5V
1.9
ns
Lead of EHOST6 with respect to HOST1-5, 7
Rising edges at 1.5V
3.9
ns
Cycle to Cycle Jitter, CPU Clocks
1000
ps
Absolute Clock Period Jitter, Other MHz Clocks,
except 14.318 MHz
-500
500
ps
EMI reduction, peaks of 5th - 19th odd harmonics
66.6 MHz clocks, LE=1
6
11
dB
Power up time, STOP# going high to all clocks stable
8
20
ms
Power on time, applied VDD to all clocks stable
12
25
ms
Note 1.
Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels
above the operating limits but below the Absolute Maximums may affect device reliability.
VDDHOST1-4, HOST5-7
VDDHOST = 2.5V
VDDHOST = 2.5V
VDDHOST = 2.5V


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