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CS3308 Datasheet(PDF) 10 Page - Cirrus Logic |
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CS3308 Datasheet(HTML) 10 Page - Cirrus Logic |
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10 / 44 page  10 DS702F1 CS3308 CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT (Inputs: Logic 0 = DGND, Logic 1 = VD, CL =20pF) 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RESET Rising Edge to Start tirs 100 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 7) thdd 0- µs SDA Setup time to SCL Rising tsud 250 - ns Rise Time of SCL and SDA trc, trd -1 µs Fall Time SCL and SDA tfc, tfd - 300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling tack 300 1000 ns t buf t hdst t lo w t hdd t high t sud Stop Start SDA SCL t irs RESET t hdst t rc t fc t sust t susp Sta rt Stop R epe a te d t rd t fd t ack Figure 1. Control Port Timing - I²C Format |
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