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AT91SAM7X256 Datasheet(PDF) 90 Page - ATMEL Corporation

No. de Pieza. AT91SAM7X256
Descripción  AT91 ARM Thumb-based Microcontrollers
Descarga  664 Pages
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Fabricante  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
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AT91SAM7X256 Datasheet(HTML) 90 Page - ATMEL Corporation

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6120D–ATARM–02-Feb-06
AT91SAM7X256/128 Preliminary
19.3
Functional Description
The Memory Controller handles the internal ASB bus and arbitrates the accesses of up to three
masters.
It is made up of:
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• An Embedded Flash Controller
The MC handles only little-endian mode accesses. The masters work in little-endian mode only.
19.3.1
Bus Arbiter
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the
bus to one of the three masters. The EMAC has the highest priority; the Peripheral DMA Control-
ler has the medium priority; the ARM processor has the lowest one.
19.3.2
Address Decoder
The Memory Controller features an Address Decoder that first decodes the four highest bits of
the 32-bit address bus and defines three separate areas:
• One 256-Mbyte address space for the internal memories
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that
return an Abort if accessed
Figure 19-2 shows the assignment of the 256-Mbyte memory areas.
Figure 19-2. Memory Areas
0x0000 0000
0x0FFF FFFF
0x1000 0000
0xEFFF FFFF
0xF000 0000
0xFFFF FFFF
256M Bytes
256M Bytes
14 x 256MBytes
3,584 Mbytes
Internal Memories
Undefined
(Abort)
Peripherals


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