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AT91SAM7X256 Datasheet(PDF) 40 Page - ATMEL Corporation

No. de Pieza. AT91SAM7X256
Descripción  AT91 ARM Thumb-based Microcontrollers
Descarga  664 Pages
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Fabricante  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
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AT91SAM7X256 Datasheet(HTML) 40 Page - ATMEL Corporation

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6120D–ATARM–02-Feb-06
AT91SAM7X256/128 Preliminary
A seventh processing mode, System Mode, does not have any banked registers. It uses the
User Mode registers. System Mode runs tasks that require a privileged processor mode and
allows them to invoke all classes of exceptions.
12.2.4.2
Status Registers
All other processor states are held in status registers. The current operating processor status is
in the Current Program Status Register (CPSR). The CPSR holds:
• four ALU flags (Negative, Zero, Carry, and Overflow)
• two interrupt disable bits (one for each type of interrupt)
• one bit to indicate ARM or Thumb execution
• five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the
CPSR of the task immediately preceding the exception.
12.2.4.3
Exception Types
The ARM7TDMI
supports five types of exception and a privileged processing mode for each type.
The types of exceptions are:
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupts (SWIs)
Exceptions are generated by internal and external sources.
More than one exception can occur in the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save state.
To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to
the PC. This can be done in two ways:
• by using a data-processing instruction with the S-bit set, and the PC as the destination
• by using the Load Multiple with Restore CPSR instruction (LDM)
12.2.5
ARM Instruction Set Overview
The ARM instruction set is divided into:
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bit[31:28]).
Table 12-2 gives the ARM instruction mnemonic list.


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