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M1025 Datasheet(PDF) 3 Page - Integrated Circuit Systems

No. de Pieza. M1025
Descripción  VCSO BASED CLOCK PLL WITH AUTOSWITCH
Descarga  14 Pages
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Fabricante  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
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M1025 Datasheet(HTML) 3 Page - Integrated Circuit Systems

 
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M1025/26 Datasheet Rev 1.0
3 of 14
Revised 28Jul2004
Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Prod uct Data Sh eet
Integrated
Circuit
Systems, Inc.
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The MR_SEL3:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1025 and M1026 are defined in
Tables 3 and 4 respectively.
M1025 M/R Divider LUT
ables 3 and 4 provide example Fin and phase
detector frequencies with 155.52MHz VCSO
devices (M1025-11-155.5200 and M1026-11-155.5200).
See “Ordering Information” on pg. 14
.
M1026 M/R Divider LUT
Phase
Locked
Loop
(PLL)
M 1025/26
SAW Delay Line
Phase
Shifter
VCSO
C
PO ST
C
PO ST
VC
nVC
R
POST
nO P_O UT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LO OP
C
LO OP
OP_IN
nOP_IN
PLL
Phase
Detector
Loop Filter
Am plifier
External
Loop Filter
Components
M R_SEL3:0
R Div
MUX
0
R EF_SEL
DIF_R EF0
nDIF_R EF0
1
M Divider
NBW
R
IN
R
IN
M / R Divider
LUT
DIF_R EF1
nDIF_R EF1
Auto
Ref Sel
0
1
LO L
Phase
Detector
REF_AC K
AUTO
LO L
FO UT
nFO UT
P_SEL1:0
P Divider
LUT
P Divider
(1, 2, or TriState)
4
2
TriState
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0 0 0 0
8
1
8
19.44
19.44
0 0 0 1
32
4
8
19.44
4.86
0 0 1 0
128
16
8
19.44
1.215
0 0 1 1
512
64
8
19.44
0.30375
0 1 0 0
2
1
2
77.76
77.76
0 1 0 1
8
4
2
77.76
19.44
0 1 1 0
32
16
2
77.76
4.86
0 1 1 1
128
64
2
77.76
1.215
1 0 0 0
1
1
1
155.52
155.52
1 0 0 1
4
4
1
155.52
38.88
1 0 1 0
16
16
1
155.52
9.72
1 0 1 1
64
64
1
155.52
2.43
1 1 0 0
Test Mode1
Note 1: Factory test mode; do not use.
N/A
N/A
N/A
1 1 0 1
1
4
0.25
622.08
155.52
1 1 1 0
4
16
0.25
622.08
38.88
1 1 1 1
16
64
0.25
622.08
9.72
Table 3: M1025 M/R Divider LUT
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0 0 0 0
4
1
4
38.88
38.88
0 0 0 1
16
4
4
38.88
9.72
0 0 1 0
64
16
4
38.88
2.43
0 0 1 1
256
64
4
38.88
0.6075
0 1 0 0
2
1
2
77.76
77.76
0 1 0 1
8
4
2
77.76
19.44
0 1 1 0
32
16
2
77.76
4.86
0 1 1 1
128
64
2
77.76
1.215
1 0 0 0
1
1
1
155.52
155.52
1 0 0 1
4
4
1
155.52
38.88
1 0 1 0
16
16
1
155.52
9.72
1 0 1 1
64
64
1
155.52
2.43
1 1 0 0
Test Mode1
Note 1: Factory test mode; do not use.
N/A
N/A
N/A
1 1 0 1
1
4
0.25
622.08
155.52
1 1 1 0
4
16
0.25
622.08
38.88
1 1 1 1
16
64
0.25
622.08
9.72
Table 4: M1026 M/R Divider LUT


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