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FWIXPEED0SE000 Datasheet(PDF) 36 Page - Intel Corporation |
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FWIXPEED0SE000 Datasheet(HTML) 36 Page - Intel Corporation |
36 / 226 page LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 38 Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 206 205 C15, B17 RxData6_0 RxData6_1 O, TS O, TS, ID Receive Data - Port 6. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. 198 197 E16, F14 RxData7_0 RxData7_1 O, TS O, TS, ID Receive Data - Port 7. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. 58 49 39 31 17 10 1 200 E4, C4, A5, B8, B12, D12, B16, E15 CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 O, TS, SL, ID Carrier Sense/Receive Data Valid - Ports 0-7. On detection of valid carrier, these signals are asserted asynchronously with respect to REFCLK. CRS_DVn is de-asserted on loss of carrier, synchronous to REFCLK. 59 50 40 32 20 11 2 201 D2, D5, D7, C8, A12, A15, A17, D17 RxER0 RxER1 RxER2 RxER3 RxER4 RxER5 RxER6 RxER7 O, TS, SL, ID Receive Error - Ports 0-7. These signals are synchronous to the respective REFCLK. Active High indicates that received code group is invalid, or that PLL is not locked. The RxER signals have the following additional function pins: RxER0 (MDIX) RxER1 (PAUSE) RxER2 (PREASEL) RxER4 (FIFOSEL0) RxER5 (FIFOSEL1) RxER6 (LINKHOLD) Table 5. Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 3 of 3) Pin-Ball Designation Symbol Type1 Signal Description2,3 PQFP PBGA 1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull- Down. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. |
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