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MC9S08AW60 Datasheet(PDF) 58 Page - Freescale Semiconductor, Inc

No. de Pieza. MC9S08AW60
Descripción  Microcontrollers
Descarga  324 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC9S08AW60 Datasheet(HTML) 58 Page - Freescale Semiconductor, Inc

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Chapter 4 Memory
MC9S08AW60 Data Sheet, Rev 2
58
Freescale Semiconductor
4.6
FLASH Registers and Control Bits
The FLASH module has nine 8-bit registers in the high-page register space, three locations in the
nonvolatile register space in FLASH memory which are copied into three corresponding high-page control
registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and
Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and
control bits only by their names. A Freescale-provided equate or header file normally is used to translate
these names into the appropriate absolute addresses.
4.6.1
FLASH Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
if PRDIV8 = 0 — fFCLK = fBus ÷ ([DIV5:DIV0] + 1)
Eqn. 4-1
if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × ([DIV5:DIV0] + 1))
Eqn. 4-2
Table 4-7 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
76543210
R
DIVLD
PRDIV8
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
W
Reset
00000000
= Unimplemented or Reserved
Figure 4-6. FLASH Clock Divider Register (FCDIV)
Table 4-6. FCDIV Register Field Descriptions
Field
Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
6
PRDIV8
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
5:0
DIV[5:0]
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5
μsto
6.7
μs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See Equation 4-1, Equation 4-2, and Table 4-6.


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