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MC9S08AW60 Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc

No. de Pieza. MC9S08AW60
Descripción  Microcontrollers
Descarga  324 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC9S08AW60 Datasheet(HTML) 68 Page - Freescale Semiconductor, Inc

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Chapter 5 Resets, Interrupts, and System Configuration
MC9S08AW60 Data Sheet, Rev 2
68
Freescale Semiconductor
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by
this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2
External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1
Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 in order for the IRQ pin to act as
the interrupt request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels
detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an
event causes an interrupt or only sets the IRQF flag which can be polled by software.
When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather than
a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is
configured to act as the IRQ input.
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
* High byte (H) of index register is not automatically stacked.
*
PROGRAM COUNTER LOW
70
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT


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