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MC9S08AW60 Datasheet(PDF) 83 Page - Freescale Semiconductor, Inc

No. de Pieza. MC9S08AW60
Descripción  Microcontrollers
Descarga  324 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC9S08AW60 Datasheet(HTML) 83 Page - Freescale Semiconductor, Inc

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Chapter 6 Parallel Input/Output
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
83
Port B pins are general-purpose I/O pins. Parallel I/O function is controlled by the port B data (PTBD) and
data direction (PTBDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTBPE), slew rate control (PTBSE), and drive strength select (PTBDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port B general-purpose I/O are shared with the ADC. Any pin enabled as an ADC input will have the
general-purpose I/O function disabled. Refer to Chapter 14, “Analog-to-Digital Converter
(S08ADC10V1)” for more information about using port B as analog inputs.
6.3.3
Port C
Figure 6-3. Port C Pin Names
Port C pins are general-purpose I/O pins. Parallel I/O function is controlled by the port C data (PTCD) and
data direction (PTCDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTCPE), slew rate control (PTCSE), and drive strength select (PTCDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port C general-purpose I/O is shared with SCI2, IIC, and MCLK. When any of these shared functions is
enabled, the direction, input or output, is controlled by the shared function and not by the data direction
register of the parallel I/O port. Also, for pins which are configured as outputs by the shared function, the
output data is controlled by the shared function and not by the port data register.
Refer to Chapter 11, “Serial Communications Interface (S08SCIV2)” for more information about using
port C pins as SCI pins.
Refer to Chapter 13, “Inter-Integrated Circuit (S08IICV1)” for more information about using port C pins
as IIC pins.
Refer to Chapter 5, “Resets, Interrupts, and System Configuration” for more information about using
PTC2 as the MCLK pin.
6.3.4
Port D
Figure 6-4. Port D Pin Names
Port D pins are general-purpose I/O pins. Parallel I/O function is controlled by the port D data (PTDD) and
data direction (PTDDD) registers which are located in page zero register space. The pin control registers,
Port C
Bit 7
653321
Bit 0
MCU Pin:
PTC6
PTC5/
RxD2
PTC4
PTC3/
TxD2
PTC2/
MCLK
PTC1/
SDA1
PTC0/
SCL1
Port D
Bit 7
654321
Bit 0
MCU Pin:
PTD7/
AD1P15/
KBI1P7
PTD6/
AD1P14/
TPM1CLK
PTD5/
AD1P13/
PTD4/
AD1P12/
TPM2CLK
PTD3/
AD1P11/
KBI1P6
PTD2/
AD1P10/
KBI1P5
PTD1/
AD1P9
PTD0/
AD1P8


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