Analog Integrated Circuit Device Data

8

Freescale Semiconductor

33976

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

SPI INTERFACE TIMING (15)

Recommended Frequency of SPI Operation

–

1.0

2.0

MHz

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (16)

–

50

167

ns

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (16)

–

50

167

ns

SI to Falling Edge of SCLK (Required Setup Time) (16)

–

25

83

ns

Required High State Duration of SCLK (Required Setup Time (16)

–

–

167

ns

Required Low State Duration of SCLK (Required Setup Time (16)

–

–

167

ns

Falling Edge of SCLK to SI (Required Hold Time) (16)

–

25

83

ns

SO Rise Time

–

25

50

ns

SO Fall Time

–

25

50

ns

SI, CS, SCLK, Incoming Signal Rise Time (17)

–

–

50

ns

SI, CS, SCLK, Incoming Signal Fall Time (17)

–

–

50

ns

Falling Edge of RST to Rising Edge of RST (Required Setup Time) (16)

–

–

3.0

µs

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (16), (18)

–

–

5.0

µs

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (16)

–

–

5.0

µs

Time from Falling Edge of CS to SO Low Impedance (19)

–

–

145

ns

Time from Rising Edge of CS to SO High Impedance (20)

–

1.3

4.0

µs

Time from Rising Edge of SCLK to SO Data Valid (21)

–

90

150

ns

Notes

15.

The 33976 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified

temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device

shall be fully functional for slower clock speeds.

16.

The maximum setup time specified for the 33976 is the minimum time needed from the microcontroller to guarantee correct operation.

17.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

18.

The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.

19.

Time required for output status data to be terminated at SO. 1.0 k

Ω load on SO

20.

Time required for output status data to be available for use at SO. 1.0 k

Ω load on SO.

21.

Time required to obtain valid data out from SO following the rise of SCLK.

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V

Characteristic

Symbol

Min

Typ

Max

Units