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MC33976 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MC33976 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 40 page Analog Integrated Circuit Device Data 8 Freescale Semiconductor 33976 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS SPI INTERFACE TIMING (15) Recommended Frequency of SPI Operation fSPI – 1.0 2.0 MHz Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (16) tLEAD – 50 167 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (16) tLAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time) (16) tSISU – 25 83 ns Required High State Duration of SCLK (Required Setup Time (16) tWSCLKh – – 167 ns Required Low State Duration of SCLK (Required Setup Time (16) tWSCLKl – – 167 ns Falling Edge of SCLK to SI (Required Hold Time) (16) tSI(HOLD) – 25 83 ns SO Rise Time CL = 200 pF tRSO – 25 50 ns SO Fall Time CL = 200 pF tFSO – 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time (17) tRSI – – 50 ns SI, CS, SCLK, Incoming Signal Fall Time (17) tFSI – – 50 ns Falling Edge of RST to Rising Edge of RST (Required Setup Time) (16) tWRST – – 3.0 µs Rising Edge of CS to Falling Edge of CS (Required Setup Time) (16), (18) tCS – – 5.0 µs Rising Edge of RST to Falling Edge of CS (Required Setup Time) (16) tEN – – 5.0 µs Time from Falling Edge of CS to SO Low Impedance (19) tSO(EN) – – 145 ns Time from Rising Edge of CS to SO High Impedance (20) tSO(DIS) – 1.3 4.0 µs Time from Rising Edge of SCLK to SO Data Valid (21) 0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF tVALID – 90 150 ns Notes 15. The 33976 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall be fully functional for slower clock speeds. 16. The maximum setup time specified for the 33976 is the minimum time needed from the microcontroller to guarantee correct operation. 17. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 18. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes. 19. Time required for output status data to be terminated at SO. 1.0 k Ω load on SO 20. Time required for output status data to be available for use at SO. 1.0 k Ω load on SO. 21. Time required to obtain valid data out from SO following the rise of SCLK. Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, -40°C ≤ TJ ≤ 150°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Units |
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