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MC68HC908JG16 Datasheet(PDF) 96 Page - Motorola, Inc |
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MC68HC908JG16 Datasheet(HTML) 96 Page - Motorola, Inc |
96 / 324 page System Integration Module (SIM) Technical Data MC68HC908JG16 — Rev. 1.0 96 System Integration Module (SIM) MOTOROLA 8.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 8.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 113 8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.8.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 117 8.8.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 118 8.8.3 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .119 8.2 Introduction This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing. A block diagram of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM I/O registers. The SIM is responsible for: • Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and COP timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Table 8-1 shows the internal signal names used in this section. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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