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SDA2546-5 Datasheet(PDF) 3 Page - Siemens Semiconductor Group

No. de Pieza. SDA2546-5
Descripción  Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface
Descarga  12 Pages
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Fabricante  SIEMENS [Siemens Semiconductor Group]
Página de inicio  http://www.siemens.com/
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SDA2546-5 Datasheet(HTML) 3 Page - Siemens Semiconductor Group

 
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Semiconductor Group
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SDA 2546-5
Memory Reprogramming
The reprogramming cycle of a memory word comprises an erase and a subsequent write process.
During erase, all eight bits of the selected word are set into "1" state. During the write process, "0"
states are generated according to the information in the internal data register, i.e. according to the
third input control word.
After the 27th and the last clock of the control word input, the active programming process is started
by the stop condition. The active reprogramming process is executed under on-chip control and can
be terminated by addressing the device via SCL and SDA.
The time required for reprogramming depends on component deviation and data patterns.
Therefore, with rated supply voltage the erase/write process is max. 20 ms, or typically, 10 ms. For
the input of a data word without write request (write request is defined as data bit in the data register
set to "0"), the write process is suppressed and the programming time is shortened. During a
subsequent programming of an already erased memory address, the erase process is suppressed
again, so that the reprogramming time is also shortened.
Switch-On and Chip Reset
After the supply voltage
VCC has been connected, the data output will be in the high impedance
mode. As a rule, the first operating mode to be entered should be the read process of a word
address. Subsequent to the data output and to the stop condition, the internal control logic is reset.
In case of a subsequent active programming operation, however, the stop condition will not reset
the control logic.
Chip Erase
To erase the entire memory the control word CS/E is entered, the address register is loaded with
address 0 and the data register with FF (hex), respectively. Immediately prior to generating the stop
condition, the input TP2 is connected from 0 to 5 V. The subsequent stop condition initiates the chip
erase. As soon as the erase procedure has terminated, TP2 is again connected to 0 V.


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