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NM27C512Q200 Datasheet(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza NM27C512Q200
Descripción Electrónicos  524,288-Bit (64K x 8) High Performance CMOS EPROM
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

NM27C512Q200 Datasheet(HTML) 7 Page - National Semiconductor (TI)

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Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Ta-
ble I It should be noted that all inputs for the six modes are
at TTL levels The power supplies required are VCC and
OEVPP The OEVPP power supply must be at 1275V dur-
ing the three programming modes and must be at 5V in the
other three modes The VCC power supply must be at 625V
during the three programming modes and at 5V in the other
three modes
Read Mode
The EPROM has two control functions both of which must
be logically active in order to obtain data at the outputs
Chip Enable (CEPGM) is the power control and should be
used for device selection Output Enable (OEVPP)isthe
output control and should be used to gate data to the output
pins independent of device selection Assuming that ad-
dresses are stable address access time (tACC) is equal to
the delay from CE to output (tCE) Data is available at the
outputs tOE after the falling edge of OE assuming that CE
has been low and addresses have been stable for at least
tACC–tOE
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99% from 385 mW to 055 mW
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CEPGM input When in standby
mode the outputs are in a high impedance state indepen-
dent of the OE input
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input When in output disable all cir-
cuitry is enabled except the outputs are in a high imped-
ance state (TRI-STATE)
Output OR-Typing
Because the EPROM is usually used in larger memory ar-
rays National has provided a 2-line control function that
accommodates this use of multiple memory connections
The 2-line control function allows for
a) the lowest possible memory power dissipation and
b) complete assurance that output bus contention will not
occur
To most efficiently use these two control lines it is recom-
mended that CEPGM be decoded and used as the primary
device selecting function while OEVPP be made a com-
mon connection to all devices in the array and connected to
the READ line from the system control bus
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are ac-
tive only when data is desired from a particular memory de-
vice
Programming
CAUTION Exceeding 14V on pin 22 (OEVPP) will damage
the EPROM
Initially and after each erasure all bits of the EPROM are in
the ‘‘1’s’’ state Data is introduced by selectively program-
ming ‘‘0’s’’ into the desired bit locations Although only
‘‘0’s’’ will be programmed both ‘‘1’s’’ and ‘‘0’s’’ can be pre-
sented in the data word The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure
The EPROM is in the programming mode when the OEVPP
is at 1275V It is required that at least a 01 mF capacitor be
placed across VCC to ground to suppress spurious voltage
transients which may damage the device The data to be
programmed is applied 8 bits in parallel to the data output
pins The levels required for the address and data inputs are
TTL
When the address and data are stable an active low TTL
program pulse is applied to the CEPGM input A program
pulse must be applied at each address location to be pro-
grammed
The EPROM is programmed with the Fast Programming Al-
gorithm shown in
Figure 1 Each Address is programmed
with a series of 100 ms pulses until it verifies good up to a
maximum of 25 pulses Most memory cells will program with
a single 100 ms pulse
The EPROM must not be programmed with a DC signal ap-
plied to the CEPGM input
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements Like inputs of the parallel
EPROM may be connected together when they are pro-
grammed with the same data A low level TTL pulse applied
to the CEPGM input programs the paralleled EPROM
Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished Except for CEPGM all
like inputs (including OEVPP) of the parallel EPROMs may
be common A TTL low level program pulse applied to an
EPROM’s CEPGM input with OEVPP at 1275V will pro-
gram that EPROM A TTL high level CEPGM input inhibits
the other EPROMs from being programmed
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed The
verify is accomplished with OEVPP and CE at VIL Data
should be verified TDV after the falling edge of CE
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure Covering the window will
also prevent temporary functional failure due to the genera-
tion of photo currents
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid
in programming When the device is inserted in an EPROM
programmer socket the programmer reads the code and
then automatically calls up the specific programming algo-
rithm for the part This automatic programming control is
only possible with programmers which have the capability of
reading the code
The Manufacturer’s Identification code shown in Table II
specifically identifies the manufacturer and device type The
code for NM27C512 is ‘‘8F85’’ where ‘‘8F’’ designates that
it is made by National Semiconductor and ‘‘85’’ designates
a 512K part
The code is accessed by applying 12V g05V to address
pin A9 Addresses A1 – A8 A10 – A16 and all control pins
7


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