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IDT74ALVCH374 Datasheet(PDF) 1 Page - Integrated Device Technology

No. de Pieza. IDT74ALVCH374
Descripción  3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
Descarga  6 Pages
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Fabricante  IDT [Integrated Device Technology]
Página de inicio  http://www.idt.com
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IDT74ALVCH374 Datasheet(HTML) 1 Page - Integrated Device Technology

   
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH374
3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE
MARCH 1999
1999
Integrated Device Technology, Inc.
DSC-4473/-
c
IDT74ALVCH374
ADVANCE
INFORMATION
EXTENDED COMMERCIAL TEMPERATURE RANGE
Functional Block Diagram
3.3V CMOS OCTAL POSITIVE
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This octal postive edge-triggered D-type flip-flop is built using advanced
dual metal CMOS technology. The ALVCH374 device is particularly
suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. On the positive transition of the clock (CLK)
input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (
OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without interface or pullup
components.
OE does not affect internal operations of the latch. Old data
can be retained or new data can be entered while the outputs are in the
high-impedance state.
The ALVCH374 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH374 has a “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
FEATURES:
0.5 MICRON CMOS Technology
–Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm TSSOP packages
Extended commercial range of -40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 2.7V to 3.6V, Extended Range
–VCC = 2.5V ±0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH374:
High Output Drivers: ±24mA
Suitable for heavy loads
1
Q
11
2
OE
TO SEVEN OTHER CHANNELS
1
CLK
1
D
C1
1
D
3


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