5

FN8231.5

October 23, 2006

Timing Diagrams

Bus Timing

Write Cycle Timing

STOP Condition Hold Time for

Read, or Volatile Only Write

From SDA rising edge to SCL

falling edge. Both crossing 70%

600

ns

Output Data Hold Time

From SCL falling edge crossing

0ns

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip.

10

400

pF

Cpin

SDA, and SCL Pin Capacitance

10

pF

Non-volatile Write Cycle Time

12

20

ms

10

NOTES:

7. Specified at +25°C.

9. Parameter is not 100% tested.

sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.

AC Electrical Specifications

(Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

SCL

SDA

8TH BIT OF LAST BYTE

ACK

STOP

CONDITION

START

CONDITION

ISL12026