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IDT74FCT16952AT Datasheet(PDF) 6 Page - Integrated Device Technology

No. de Pieza. IDT74FCT16952AT
Descripción  FAST CMOS 16-BIT REGISTERED TRANSCEIVER
Descarga  7 Pages
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Fabricante  IDT [Integrated Device Technology]
Página de inicio  http://www.idt.com
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IDT74FCT16952AT Datasheet(HTML) 6 Page - Integrated Device Technology

   
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6
INDUSTRIALTEMPERATURERANGE
IDT74FCT16925AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
Pulse
Generator
R T
D.U.T.
V CC
V IN
CL
V OUT
50pF
500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIM IN G
INPUT
ASYNC HR ONOUS C ONTROL
PRES ET
CLEA R
ETC .
SYNCHR ON OUS CONTROL
tSU
tH
tREM
tSU
tH
PRES ET
CLEA R
CLOCK ENABLE
ETC .
HIGH-LOW -H IGH
PU LSE
LOW -HIGH-LOW
PU LSE
tW
1.5V
1.5V
SAM E PHASE
INPUT TRAN SITION
3V
1.5V
0V
1.5V
VOH
tPLH
OU TPU T
OPPOSITE P HASE
INPUT TRAN SITION
3V
1.5V
0V
tPLH
tPHL
tPHL
VOL
CONTROL
IN PU T
3V
1.5V
0V
3.5V
0V
OUTPU T
NORM ALLY
LOW
OUTPU T
NORM ALLY
HIGH
SW ITCH
CLOSED
SW ITC H
OPEN
VOL
0.3V
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
1.5V
ENABLE
D ISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.


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