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TU24C04 Datasheet(Hoja de datos) 4 Page - List of Unclassifed Manufacturers

No. de Pieza. TU24C04
Descripción  CMOS I2C 2-WIRE BUS 4K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 512 X 8 BIT EEPROM
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Fabricante  ETC2 [List of Unclassifed Manufacturers]
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24C04
PRODUCT INTRODUCTION
Turbo IC, Inc.
DEVICE ADDRESSING:
Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (B8) (R/W) to ac-
cess the selected Turbo IC 24C04 for a read or write opera-
tion. A1 and A2 are the device address select bits which have
to match the A1 and A2 pin inputs on the 24C04 device. The
B[8] bit is the most significant bit of the memory address.
The (R/W) bit is a high (1) for read and low (0) for write.
DATA INPUT DURING WRITE OPERATION:
During the write operation, the Turbo IC 24C04 latches the
SDA bus signal on the rising edge of the SCL clock.
DATA OUTPUT DURING READ OPERATION:
During the read operation, the Turbo IC 24C04 serially shifts
the data onto the SDA bus on the falling edge of the SCL
clock.
MEMORY ADDRESSING:
The memory address is sent by the master in the form of 2
bytes. Device address A2 and memory address bits B[8],
are included in the device address byte. The remaining
memory address bits B[7:0] are included in the second byte.
The memory address byte can only be sent as part of a write
operation.
BYTE WRITE OPERATION:
The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (B8) 0, followed by the memory address byte, fol-
lowed by one data byte, followed by an acknowledge, then a
stop condition. After each byte transfer, the Turbo IC 24C04
acknowledges the successful data transmission by pulling
the SDA bus low. The stop condition starts the internal
EEPROM write cycle, and all inputs are disabled until the
completion of the write cycle.
4
PAGE WRITE OPERATION:
The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (B8) 0, followed by the memory address byte, fol-
lowed by up to 16 data bytes, followed by an acknowledge,
then a stop condition. After each byte transfer, the Turbo IC
24C04 acknowledges the successful data transmission by
pulling SDA low. After each data byte transfer, the memory
address counter is automatically incremented by one. The
stop condition starts the internal EEPROM write cycle only if
the stop condition occurs in the clock cycle immediately fol-
lowing the acknowledge (10th clock cycle). All inputs are dis-
abled until the completion of the write cycle.
POLLING ACKNOWLEDGE:
During the internal write cycle of a write operation in the Turbo
IC 24C04, the completion of the write cycle can be detected
by polling acknowledge. The master starts acknowledge poll-
ing by issuing a start condition, then followed by the device
address byte 1010 (A2) (A1) (B8) 0. If the internal write cycle
is finished, the Turbo IC 24C04 acknowledges by pulling the
SDA bus low. If the internal write cycle is still ongoing, the
Turbo IC 24C04 does not acknowledge because it’s inputs
are disabled. Therefore, the device will not respond to any
command. By using polling acknowledge, the system delay
for write operations can be reduced. Otherwise, the system
needs to wait for the maximum internal write cycle time, tWC,
given in the spec.
POWER ON RESET:
The Turbo IC 24C04 has a Power On Reset circuit (POR) to
prevent data corruption and accidental write operations dur-
ing power up. On power up, the internal reset signal is on
and the Turbo IC 24C04 will not respond to any command
until the VCC voltage has reached the POR threshold value.




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