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W83194BR-645 Datasheet(PDF) 2 Page - Winbond |
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W83194BR-645 Datasheet(HTML) 2 Page - Winbond |
2 / 24 page W83194BR-645 - II - Table of Contents- 1. GENERAL DESCRIPTION ..........................................................................................................1 2. FEATURES ..................................................................................................................................1 3. PIN CONFIGURATION ................................................................................................................2 4. BLOCK DIAGRAM .......................................................................................................................2 5. PIN DESCRIPTION......................................................................................................................3 5.1 Crystal I/O ........................................................................................................................3 5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs .......................................................................3 5.3 I2C Control Interface........................................................................................................4 5.4 Fixed Frequency Outputs ................................................................................................4 5.5 Power Management Pins.................................................................................................5 5.6 Power Pins.......................................................................................................................5 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................7 7. I 2C CONTROL AND STATUS REGISTERS................................................................................9 7.1 Register 4: Frequency Select Register (default = 0) .......................................................9 7.2 Register 5: CPU, SDRAM Clock Register (1 = Enable, 0 = Stopped).............................9 7.3 Register 6 PCI Clock Register (1 = Enable, 0 = Stopped) ............................................11 7.4 Register 7 48 MHz, ZCLK, REF Clock Register (1 = Enable, 0 = Stopped)..................11 7.5 Register 8: AGP Control Register (1 = Enable, 0 = Stopped) .......................................11 7.6 Register 9: Watchdog Control Register .........................................................................13 7.7 Register 10: Watchdog Timer Register .........................................................................13 7.8 Register 11: M/N Program Register...............................................................................14 7.9 Register 12: M/N Program Register...............................................................................14 7.10 Register 13: Spread Spectrum Programming Register .................................................14 7.11 Register 14: Divisor and Step-less Enable Control Register.........................................15 7.12 Register 15: CPU_ZCLK Skew Control Register...........................................................15 7.13 Register 16: CPU_AGP_SKEW.....................................................................................15 7.14 Register 17: Skew Control Register...............................................................................16 7.15 Register 18: Winbond Chip ID Register (Read Only) ....................................................16 7.16 Register 19: Winbond Chip ID Register (Read Only) ....................................................16 7.17 Ratio Selection Table.....................................................................................................17 8. ACCESS INTERFACE ...............................................................................................................19 8.1 Block Write Protocol ......................................................................................................19 8.2 Block Read Protocol ......................................................................................................19 8.3 Byte Write Protocol ........................................................................................................19 8.4 Byte Read Protocol........................................................................................................19 9. ORDERING INFORMATION......................................................................................................20 10. HOW TO READ THE TOP MARKING.......................................................................................20 11. PACKAGE DRAWING AND DIMENSIONS...............................................................................21 12. REVISION HISTORY .................................................................................................................22 |
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