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W39V040A Datasheet(PDF) 3 Page - Winbond

No. de Pieza. W39V040A
Descripción  512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE
Descarga  34 Pages
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Fabricante  WINBOND [Winbond]
Página de inicio  http://www.winbond.com
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W39V040A Datasheet(HTML) 3 Page - Winbond

 
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W39V040A
Publication Release Date: December 19, 2002
- 3 -
Revision A2
6. FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, and the other is
LPC interface mode. The MODE pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When
MODE pin is set to high position, the device is in the Programmer mode; while the MODE pin is set to
low position, it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash
parts with 8 data lines. But the row and column address inputs are multiplexed. The row address is
mapped to the higher internal address A[18:11]. And the column address is mapped to the lower internal
address A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.0. Through
the LAD[3:0] and #LFRAM to communicate with the system chipset .
Read(Write) Mode
In Programmer interface mode, the read(write) operation of the W39V040A is controlled by #OE (#WE).
The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when #OE is high. As in the LPC interface the "bit 1 of CYCLE TYPE+DIR" determines mode, the read
or write. Refer to the timing waveforms for further details.
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is
in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be
at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read
or standby mode, it depends on the control signals.
Boot Block Operation and Hardware Protection at Initial - #TBL and #WP
There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this
device can be locked as boot block, which can be used to store boot codes. It is located in the last
16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex).
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not
be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be
programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address 7FFF2(hex). If the DQ0/DQ1 output
data is "1," the 64Kbytes/16Kbytes boot block programming lockout feature will be activated; if the
DQ0/DQ1 output data is "0," the lockout feature will be inactivated and the boot block can be
erased/programmed. But the hardware protection will override the software lock setting, i.e., while the
#TBL pin is trapped at low state, the top boot block cannot be programmed/erased whether the output
data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL will lock the whole 64Kbytes top boot


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