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MC908QC8CDXER Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc |
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MC908QC8CDXER Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 274 page  Analog-to-Digital Converter (ADC10) Module MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 56 Freescale Semiconductor 3.8.2 ADC10 Result High Register (ADRH) This register holds the MSBs of the result and is updated each time a conversion completes. All other bits read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with ADRL. 3.8.3 ADC10 Result Low Register (ADRL) This register holds the LSBs of the result. This register is updated each time a conversion completes. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion result will be lost. In 8-bit mode, there is no interlocking with ADRH. 3.8.4 ADC10 Clock Register (ADCLK) This register selects the clock frequency for the ADC10 and the modes of operation. Bit 7 654321 Bit 0 Read: 00000000 Write: Reset: 00000000 = Unimplemented Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode Bit 7 654321 Bit 0 Read: 000000 AD9 AD8 Write: Reset: 00000000 = Unimplemented Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode Bit 7 654321 Bit 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Reset: 00000000 = Unimplemented Figure 3-6. ADC10 Data Register Low (ADRL) Bit 7 654321 Bit 0 Read: ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN Write: Reset: 00000000 Figure 3-7. ADC10 Clock Register (ADCLK) |
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