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MC908QC8CDZER Datasheet(PDF) 81 Page - Freescale Semiconductor, Inc |
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MC908QC8CDZER Datasheet(HTML) 81 Page - Freescale Semiconductor, Inc |
81 / 274 page Functional Description MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 81 When set, the IMASK bit in INTSCR masks the IRQ interrupt request. A latched interrupt request is not presented to the interrupt priority logic unless IMASK is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including the IRQ interrupt request. A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch, software clear, or reset clears the IRQ latch. Figure 7-2. IRQ Module Block Diagram 7.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of the following actions must occur to clear the IRQ interrupt request: • Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active. • IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK in INTSCR. The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to ACK prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to ACK latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the IRQ vector address. The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order. The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. Use the BIH or BIL instruction to read the logic level on the IRQ pin. IMASK DQ CK CLR IRQ HIGH INTERRUPT TO MODE SELECT LOGIC REQUEST VDD MODE VOLTAGE DETECT IRQF TO CPU FOR BIL/BIH INSTRUCTIONS RESET VDD INTERNAL PULLUP DEVICE ACK IRQ SYNCHRONIZER IRQ VECTOR FETCH DECODER IRQ LATCH |
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