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MC908QC4MDSER Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc |
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MC908QC4MDSER Datasheet(HTML) 82 Page - Freescale Semiconductor, Inc |
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82 / 274 page  External Interrupt (IRQ) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 82 Freescale Semiconductor 7.3.2 MODE = 0 If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. NOTE When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. 7.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests. 7.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 7.5.1 Wait Mode The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of wait mode. 7.5.2 Stop Mode The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of stop mode. 7.6 IRQ Module During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. |
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