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MB91482 Datasheet(PDF) 1 Page - Fujitsu Component Limited.

No. de Pieza. MB91482
Descripción  32-bit proprietary Microcontrollers CMOS
Descarga  88 Pages
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Fabricante  FUJITSU [Fujitsu Component Limited.]
Página de inicio  http://edevice.fujitsu.com/fmd/en/index.html
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MB91482 Datasheet(HTML) 1 Page - Fujitsu Component Limited.

 
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DS07-16901-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
“Check Sheet” is seen at the following support page
URL : http://jp.fujitsu.com/microelectronics/products/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
32-bit proprietary Microcontrollers
CMOS
FR60 MB91470/480 Series
MB91482/F475/F478/F479/F487
MB91FV470
■ DESCRIPTION
The MB91470/480 series is Fujitsu's general-purpose 32-bit RISC microcontroller, which is designed for
embedded control applications that require high-speed processing performance.
This series uses the FR60 CPU, which is compatible with the FR* family of CPUs.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
• FR60 CPU
• 32-bit RISC, load/store architecture, five-stage pipeline
• Operating frequency of 80 MHz (PLL clock multiplied)
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed : one instruction per cycle
• Memory-to-memory transfer, bit processing, barrel shift instructions, etc. :
instructions suitable for embedded applications
• Function entry and exit instructions, multi load/store instructions of register contents :
instructions compatible with C language.
• Register interlock function to facilitate assembly-language coding
• Built-in multiplier/instruction-level support
• Signed 32-bit multiplication : 5 cycles
• Signed 16-bit multiplication : 3 cycles
• Interrupts (save PC and PS) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instructions compatible with the FR family
(Continued)


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