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CS8900A-IQ Datasheet(PDF) 4 Page - Cirrus Logic |
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CS8900A-IQ Datasheet(HTML) 4 Page - Cirrus Logic |
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4 / 137 page  4 DS271PP4 CS8900A Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET 3.10.4 TInterface Selection ...........................................................................................34 3.10.4.1 10BASE-T Only .................................................................................34 3.10.4.2 AUI Only ............................................................................................34 3.10.4.3 Auto-Select ........................................................................................34 3.11 10BASE-T Transceiver ...................................................................................................34 3.11.1 T10BASE-T Filters .............................................................................................34 3.11.2 TTransmitter ......................................................................................................35 3.11.3 TReceiver ..........................................................................................................35 3.11.3.1 Squelch Circuit ...................................................................................35 3.11.3.2 Extended Range ................................................................................35 3.11.4 TLink Pulse Detection ........................................................................................35 3.11.5 TReceive Polarity Detection and Correction ......................................................36 3.11.6 TCollision Detection ...........................................................................................36 3.12 Attachment Unit Interface (AUI) .....................................................................................36 3.12.1 TAUI Transmitter ...............................................................................................36 3.12.2 TAUI Receiver ...................................................................................................37 3.12.3 TCollision Detection ...........................................................................................37 3.13 External Clock Oscillator ................................................................................................37 4.0 PACKETPAGE ARCHITECTURE ..........................................................................................38 4.1 PacketPage Overview ......................................................................................................38 4.1.1 TIntegrated Memory ............................................................................................38 4.1.2 TBus Interface Registers .....................................................................................38 4.1.3 TStatus and Control Registers .............................................................................38 4.1.4 TInitiate Transmit Registers .................................................................................38 4.1.5 TAddress Filter Registers ....................................................................................38 4.1.6 TReceive and Transmit Frame Locations ............................................................38 4.2 PacketPage Memory Map ................................................................................................39 4.3 Bus Interface Registers ....................................................................................................41 4.4 Status and Control Registers ...........................................................................................46 4.4.1 TConfiguration and Control Registers .................................................................46 4.4.2 TStatus and Event Registers ...............................................................................46 4.4.3 TStatus and Control Bit Definitions ......................................................................46 4.4.3.1 Act-Once Bits .......................................................................................47 4.4.3.2 Temporal Bits .......................................................................................47 4.4.3.3 Interrupt Enable Bits and Events .........................................................47 4.4.3.4 Accept Bits ...........................................................................................47 4.4.4 TStatus and Control Register Summary ..............................................................48 4.5 Initiate Transmit Registers ................................................................................................70 4.6 Address Filter Registers ...................................................................................................71 4.7 Receive and Transmit Frame Locations ...........................................................................72 4.7.1 TReceive PacketPage Locations .........................................................................72 4.7.2 TTransmit Locations ............................................................................................72 4.8 Eight and Sixteen Bit Transfers ........................................................................................72 4.8.1 TTransferring Odd-Byte-Aligned Data .................................................................73 4.8.2 TRandom Access to CS8900A Memory ..............................................................73 4.9 Memory Mode Operation ..................................................................................................73 4.9.1 TAccesses in Memory Mode ...............................................................................73 4.9.2 TConfiguring the CS8900A for Memory Mode .....................................................73 4.9.3 TBasic Memory Mode Transmit ...........................................................................74 4.9.4 TBasic Memory Mode Receive ............................................................................74 4.9.5 TPolling the CS8900A in Memory Mode ..............................................................75 4.10 I/O Space Operation ......................................................................................................75 4.10.1 TReceive/Transmit Data Ports 0 and 1 ..............................................................75 |
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