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MC908QY1VDTE Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QY1VDTE
Descripción  Microcontrollers
Descarga  184 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC908QY1VDTE Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc

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Functional Description
MC68HC908QY/QT Family Data Sheet, Rev. 5
Freescale Semiconductor
91
11.3.1.1 Internal Oscillator Trimming
The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing
OSCTRIM value increases the clock period. Trimming allows the internal clock frequency to be set to
12.8 MHz ± 5%.
All devices are programmed with a trim value in a reserved FLASH location, $FFC0. This value can be
copied from the FLASH to the OSCTRIM register ($0038) during reset initialization.
Reset loads OSCTRIM with a default value of $80.
WARNING
Bulk FLASH erasure will set location $FFC0 to $FF and the factory
programmed value will be lost.
11.3.1.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following
steps:
1.
For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal
oscillator, set PTA4 (OSC2) as an output and drive high for several cycles. This may help the
crystal circuit start more robustly.
2.
Set CONFIG2 bits OSCOPT[1:0] according to . The oscillator module control logic will then set
OSC1 as an external clock input and, if the external crystal option is selected, OSC2 will also be
set as the clock output.
3.
Create a software delay to wait the stabilization time needed for the selected clock source (crystal,
resonator, RC) as recommended by the component manufacturer. A good rule of thumb for crystal
oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-MHz crystal, wait
approximately 1 msec.
4.
After the manufacturer’s recommended delay has elapsed, the ECGON bit in the OSC status
register (OSCSTAT) needs to be set by the user software.
5.
After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external
clock rising edges.
6.
The OSC module then switches to the external clock. Logic provides a glitch free transition.
7.
The OSC module first sets the ECGST bit in the OSCSTAT register and then stops the internal
oscillator.
NOTE
Once transition to the external clock is done, the internal oscillator will only
be reactivated with reset. No post-switch clock monitor feature is
implemented (clock does not switch back to internal if external clock dies).
11.3.2 External Oscillator
The external clock option is designed for use when a clock signal is available in the application to provide
a clock source to the microcontroller. The OSC1 pin is enabled as an input by the oscillator module. The
clock signal is used directly to create BUSCLKX4 and also divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4.So the OSC2EN bit in the port A pullup
enable register will be clear to enable PTA4 I/O functions on the pin


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