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MC908QY1VDTE Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QY1VDTE
Descripción  Microcontrollers
Descarga  184 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC908QY1VDTE Datasheet(HTML) 98 Page - Freescale Semiconductor, Inc

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Input/Output Ports (PORTS)
MC68HC908QY/QT Family Data Sheet, Rev. 5
98
Freescale Semiconductor
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
PTA[5:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
AWUL — Auto Wakeup Latch Data Bit
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally (see Chapter 4 Auto Wakeup Module (AWU)). There is no PTA6
port nor any of the associated bits such as PTA6 data register, pullup enable or direction.
KBI[5:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard interrupt control enable register
(KBIER) enable the port A pins as external interrupt pins (see Chapter 9 Keyboard Interrupt Module
(KBI)).
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Address: $0000
Bit 76
5
4
3
2
1Bit 0
Read:
R
AWUL
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Write:
Reset:
Unaffected by reset
Additional Functions:
KBI5
KBI4
KBI3
KBI2
KBI1
KBI0
R
= Reserved
= Unimplemented
Figure 12-1. Port A Data Register (PTA)
Address: $0004
Bit 7
6
54
32
1
Bit 0
Read:
R
R
DDRA5
DDRA4
DDRA3
0
DDRA1
DDRA0
Write:
Reset:
000
00
000
R= Reserved
= Unimplemented
Figure 12-2. Data Direction Register A (DDRA)


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