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MC908QT1VFQE Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc |
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MC908QT1VFQE Datasheet(HTML) 76 Page - Freescale Semiconductor, Inc |
76 / 184 page External Interrupt (IRQ) MC68HC908QY/QT Family Data Sheet, Rev. 5 76 Freescale Semiconductor 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests. 8.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 8.5.1 Wait Mode The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of wait mode. 8.5.2 Stop Mode The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of stop mode. 8.6 IRQ Module During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Chapter 13 System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 8.7 I/O Signals The IRQ module shares its pin with the keyboard interrupt, input/output ports, and timer interface modules. NOTE When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL instructions can be used to read the logic level on the IRQ pin. If the IRQ function is disabled, these instructions will behave as if the IRQ pin is a logic 1, regardless of the actual level on the pin. Conversely, when the IRQ function is enabled, bit 2 of the port A data register will always read a 0. When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor to VDD is connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E). |
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