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BUK116-50L Datasheet(PDF) 5 Page - NXP Semiconductors

No. de pieza BUK116-50L
Descripción Electrónicos  Logic level TOPFET SMD version of BUK106-50L/S
Download  13 Pages
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Fabricante Electrónico  PHILIPS [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

BUK116-50L Datasheet(HTML) 5 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
Logic level TOPFET
BUK116-50L/S
SMD version of BUK106-50L/S
INPUT CHARACTERISTICS
T
mb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Normal operation
V
IS(TO)
Input threshold voltage
V
DS = 5 V; ID = 1 mA
1.0
1.5
2.0
V
T
mb = 150 ˚C
0.5
-
-
V
I
IS
Input current
V
IS = 10 V
-
10
100
nA
V
(CL)IS
Input clamp voltage
I
I = 1 mA
11
13
-
V
Overload protection latched
R
ISL
Input resistance
1
V
PS = 5 V
I
I = 5 mA;
-
55
-
T
mb = 150 ˚C
-
95
-
V
PS = 10 V
I
I = 5 mA;
-
35
-
T
mb = 150 ˚C
-
60
-
Application information
External input resistances for
(see figure 29)
R
IS
internal overvoltage clamping
2
R
I = ∞ Ω;VDS > 30 V
100
-
-
R
I
internal overload protection
3
R
IS = ∞ Ω;VII = 5 V
1
-
-
k
V
II = 10 V
2
-
-
k
SWITCHING CHARACTERISTICS
T
mb = 25 ˚C;
R
I = 50 Ω; RIS = 50 Ω (see figure 29); resistive load RL = 10 Ω.
For waveforms see figure 28.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
t
d on
Turn-on delay time
V
DD = 15 V; VIS: 0 V ⇒ 10 V
-
10
-
ns
t
r
Rise time
-
35
-
ns
t
d off
Turn-off delay time
V
DD = 15 V; VIS: 10 V ⇒ 0 V
-
280
-
ns
t
f
Fall time
-
120
-
ns
CAPACITANCES
T
mb = 25 ˚C; f = 1 MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
C
iss
Input capacitance
V
DS = 25 V; VIS = 0 V
-
1250
1800
pF
C
oss
Output capacitance
V
DS = 25 V; VIS = 0 V
-
650
1000
pF
C
rss
Reverse transfer capacitance
V
DS = 25 V; VIS = 0 V
-
150
250
pF
C
pso
Protection supply pin
V
PS = 10 V
-
30
-
pF
capacitance
C
fso
Flag pin capacitance
V
FS = 10 V; VPS = 0 V
-
20
-
pF
1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates.
The external drive circuit should be such that the input voltage does not exceed V
IS(TO) minimum when the overload protection has
operated. Refer also to figure for latched input characteristics.
2 Applications using a lower value for R
IS would require external overvoltage protection.
3 For applications requiring a lower value for R
I, an external overload protection strategy is possible using the flag pin to ‘tell’ the control circuit to
switch off the input.
July 1996
5
Rev 1.000


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