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ADSP-BF533SKBCZ600 Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-BF533SKBCZ600 Datasheet(HTML) 8 Page - Analog Devices |
8 / 60 page Rev. D | Page 8 of 60 | September 2006 ADSP-BF533 • CEC interrupt pending register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 8. • SIC interrupt mask register (SIC_IMASK) – This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servic- ing the event. • SIC interrupt status register (SIC_ISR) – As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. • SIC interrupt wakeup enable register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more infor- mation, see Dynamic Power Management on Page 11.) Because multiple interrupt sources can map to a single general- purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND reg- ister contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the proces- sor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general- purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. DMA CONTROLLERS The ADSP-BF533 processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor’s internal memories and any of its DMA- capable peripherals. Additionally, DMA transfers can be accom- plished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous mem- ory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The ADSP-BF533 processor DMA controller supports both 1-dimensional (1-D) and 2-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de-interleaved on-the-fly. Examples of DMA types supported by the ADSP-BF533 proces- sor DMA controller include: • A single, linear buffer that stops upon completion • A circular, autorefreshing buffer that interrupts on each full or fractionally full buffer Table 3. System Interrupt Controller (SIC) Peripheral Interrupt Event Default Mapping PLL Wakeup IVG7 DMA Error IVG7 PPI Error IVG7 SPORT 0 Error IVG7 SPORT 1 Error IVG7 SPI Error IVG7 UART Error IVG7 Real-Time Clock IVG8 DMA Channel 0 (PPI) IVG8 DMA Channel 1 (SPORT 0 Receive) IVG9 DMA Channel 2 (SPORT 0 Transmit) IVG9 DMA Channel 3 (SPORT 1 Receive) IVG9 DMA Channel 4 (SPORT 1 Transmit) IVG9 DMA Channel 5 (SPI) IVG10 DMA Channel 6 (UART Receive) IVG10 DMA Channel 7 (UART Transmit) IVG10 Timer 0 IVG11 Timer 1 IVG11 Timer 2 IVG11 PF Interrupt A IVG12 PF Interrupt B IVG12 DMA Channels 8 and 9 (Memory DMA Stream 1) IVG13 DMA Channels 10 and 11 (Memory DMA Stream 0) IVG13 Software Watchdog Timer IVG13 |
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