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ADSP-TS202SABP-050 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-TS202SABP-050 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 48 page  Rev. C | Page 10 of 48 | December 2006 ADSP-TS202S POWER DOMAINS The ADSP-TS202S processor has separate power supply con- nections for internal logic (VDD), analog circuits (VDD_A), I/O buffer (VDD_IO), and internal DRAM (VDD_DRAM) power supply. Note that the analog (VDD_A) supply powers the clock generator PLLs. To produce a stable clock, systems must provide a clean power supply to power input VDD_A. Designs must pay critical attention to bypassing the VDD_A supply. FILTERING REFERENCE VOLTAGE AND CLOCKS Figure 6 and Figure 7 show possible circuits for filtering VREF, and SCLK_VREF. These circuits provide the reference voltages for the switching voltage reference and system clock reference. DEVELOPMENT TOOLS The ADSP-TS202S processor is supported with a complete set of CROSSCORE ®† software and hardware development tools, including Analog Devices emulators and VisualDSP++ ®‡ devel- opment environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS202S processor. The VisualDSP++ project management environment lets programmers develop and debug an application. This environ- ment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for theses tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical repre- sentation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the pro- grammer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can • View mixed C/C++ and assembly code (interleaved source and object information) • Insert breakpoints • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution • Perform linear or statistical profiling of program execution • Fill, dump, and graphically plot the contents of memory • Perform source level debugging • Create custom debugger windows The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC processor development tools, including the color syntax high- lighting in the VisualDSP++ editor. This capability permits programmers to • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the mem- ory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, Figure 6. VREF Filtering Scheme Figure 7. SCLK_VREF Filtering Scheme † CROSSCORE is a registered trademark of Analog Devices, Inc. ‡ VisualDSP++ is a registered trademark of Analog Devices, Inc. VDD_IO VSS VREF R1 R2 C1 C2 R1: 2k SERIES RESISTOR (±1%) R2: 2.55k SERIES RESISTOR (±1%) C1: 1 F CAPACITOR (SMD) C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS CLOCK DRIVER VOLTAGE OR VDD_IO VSS SCLK_VREF R1 R2 C1 C2 R1: 2k SERIES RESISTOR (±1%) R2: 2.55k SERIES RESISTOR (±1%) C1: 1 F CAPACITOR (SMD) C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS *IF CLOCK DRIVER VOLTAGE > V DD_IO * |
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