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ADSP-BF532WBSTZ-4A Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-BF532WBSTZ-4A Datasheet(HTML) 6 Page - Analog Devices |
6 / 60 page Rev. D | Page 6 of 60 | August 2006 ADSP-BF531/ADSP-BF532 The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully popu- lated with 1M byte of memory. I/O Memory Space Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one of which contains the control MMRs for all core functions, and the other of which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The ADSP-BF531/ADSP-BF532 processor contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF531/ADSP-BF532 processor is configured to boot from boot ROM memory space, the processor starts exe- cuting from the on-chip boot ROM. For more information, see Booting Modes on Page 14. Event Handling The event controller on the ADSP-BF531/ADSP-BF532 proces- sor handles all asynchronous and synchronous events to the processor. The ADSP-BF531/ADSP-BF532 processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: • Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset – This event resets the processor. • Nonmaskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. Figure 2. Blackfin Processor Core SEQUENCER ALIGN DECODE LOOP BUFFER 16 16 8 88 8 40 40 A0 A1 BARREL SHIFTER DATA ARITHMETIC UNIT CONTROL UNIT R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.H R0.L ASTAT 40 40 32 32 32 32 32 32 32 LD0 LD1 SD DAG0 DAG1 ADDRESS ARITHMETIC UNIT I3 I2 I1 I0 L3 L2 L1 L0 B3 B2 B1 B0 M3 M2 M1 M0 SP FP P5 P4 P3 P2 P1 P0 DA1 DA0 32 32 32 PREG RAB 32 |
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