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ADSP-BF531WBSTZ-4A Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-BF531WBSTZ-4A Datasheet(HTML) 1 Page - Analog Devices |
1 / 60 page a Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin® Embedded Processor ADSP-BF531/ADSP-BF532 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. FEATURES Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of pro- gramming and compiler-friendly support Advanced debug, trace, and performance monitoring 0.8 V to 1.2 V core VDD with on-chip voltage regulation 1.8 V, 2.5 V, and 3.3 V compliant I/O 160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead LQFP packages MEMORY Up to 84K bytes of on-chip memory: 16K bytes of instruction SRAM/Cache 32K bytes of instruction SRAM 32K bytes of data SRAM/Cache 4K bytes of scratchpad SRAM Two dual-channel memory DMA controllers Memory management unit providing memory protection External memory controller with glueless support for SDRAM, SRAM, FLASH, and ROM Flexible memory booting options from SPI® and external memory PERIPHERALS Parallel peripheral interface PPI/GPIO, supporting ITU-R 656 video data formats Two dual-channel, full duplex synchronous serial ports, sup- porting eight stereo I 2S channels 12-channel DMA controller SPI-compatible port Three timer/counters with PWM support UART with support for IrDA® Event handler Real-time clock Watchdog timer Debug/JTAG interface On-chip PLL capable of 0.5 to 64 frequency multiplication Core timer Figure 1. Functional Block Diagram VOLTAGE REGULATOR DMA CONTROLLER EVENT CONTROLLER/ CORE TIMER REAL-TIME CLOCK UART PORT IrDA TIMER0, TIMER1, TIMER2 PPI / GPIO SERIAL PORTS (2) SPI PORT EXTERNAL PORT FLASH, SDRAM CONTROL BOOT ROM JTAG TEST AND EMULATION WATCHDOG TIMER L1 INSTRUCTION MEMORY L1 DATA MEMORY MMU CORE/SYSTEM BUS INTERFACE B |
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