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ABSOLUTE MAXIMUM RATINGS

TYPICAL DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

TPA3101D2

SLOS473A – DECEMBER 2005 – REVISED FEBRUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

UNIT

Supply voltage

AVCC, PVCC

–0.3 V to 30 V

SHUTDOWN, MUTE

Input voltage

GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,

–0.3 V to VREG + 0.5 V

SYNC

Continuous total power dissipation

See Dissipation Rating Table

Operating free-air temperature range

–40

°C to 85°C

–40

°C to 150°C

Storage temperature range

–65

°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

Load Resistance

3.2

Ω Minimum

±2 kV

Electrostatic discharge

±200 V

±500 V

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The TPA3101D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected

to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection

shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical

Briefs SLMA002 for more information about using the HTQFP thermal pad.

(3)

In accordance with JEDEC Standard 22, Test Method A114-B.

(4)

In accordance with JEDEC Standard 22, Test Method A115-A

(5)

In accordance with JEDEC Standard 22, Test Method C101-A

PACKAGE

DERATING FACTOR

48-pin RGZ (QFN)

4.39 W

35.1 mW/

2.81 W

2.28 W

48-pin PHP (HTQFP)

4.82 W

38.6 mW/

3.09 W

2.51 W

(1)

This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must

be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about

using the QFN thermal pad.

(2)

This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must

be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the

HTQFP thermal pad.

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Supply voltage

PVCC, AVCC

10

26

V

SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,

High-level input voltage

2

V

SYNC

SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,

Low-level input voltage

0.8

V

SYNC

125

75

High-level input current

µA

2

2

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