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LNBP21 Datasheet(PDF) 5 Page - STMicroelectronics

No. de Pieza. LNBP21
Descripción  LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
Descarga  24 Pages
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Fabricante  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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LNBP21 Datasheet(HTML) 5 Page - STMicroelectronics

 
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Figure 3: Typical Application Circuit
(*) Set to GND if not used
(**) filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.x, not needed if bidirectional DiSEqCTM 2.x is
not implemented (see DiSEqC implementation note)
(***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel MosFet, needed for the DC/DC converter,
in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel MosFet (STN4NF03L or similar)
I2C BUS INTERFACE
Data transmission from main µP to the LNBP21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).
DATA VALIDITY
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
START AND STOP CONDITIONS
As shown in fig. 4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
conditions must be sent before each START
condition.
BYTE FORMAT
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig.
4).
The
peripheral
(LNBP21)
that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBP21 won't generate the acknowledge if
the VCC supply is below the Undervoltage Lockout
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBP21, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
270µH
15 ohm
see Note 2
Vup
Gate
Vin
12V
L1=22µH
Sense
C2
220µF
Vcc
LT1
Master STB
Vo
LT2
DETIN
(Note 1)
C8
10nF
to LNB
SDA
SCL
DSQOUT
DSQIN(Note 1)
ADDRESS
Byp
C5
470nF
GND
0<Vaddr<V
Byp
EXTM
C6
10nF
270µH
15 ohm
see Note 2
Vup
Gate
Vin
12V
L1=22µH
Sense
C2
220µF
Vcc
LT1
Master STB
Vo
LT2
DETIN
(Note 1)
C8
10nF
to LNB
SDA
SCL
DSQOUT
DSQIN(Note 1)
ADDRESS
Byp
C5
470nF
GND
0<Vaddr<V
Byp
EXTM
C6
10nF
Rsc
0.1 Ω
C3
470nF
Ceramic
D1 1N4001
C1
220µF
C4
470nF
Ceramic
D2
BAT43
C7
10nF
STS4DNFS30L
Rsc
0.1 Ω
C3
470nF
Ceramic
D1 1N4001
C1
220µF
C4
470nF
Ceramic
D2
BAT43
C7
10nF
STS4DNFS30L
IC2
(Note 3)
IC1
(Note 4)
LNBP21
Rsc
0.1 Ω
C3
470nF
Ceramic
D1 1N4001
C1
220µF
C4
470nF
Ceramic
D2
BAT43
C7
10nF
STS4DNFS30L
Rsc
0.1 Ω
C3
470nF
Ceramic
D1 1N4001
C1
220µF
C4
470nF
Ceramic
D2
BAT43
C7
10nF
STS4DNFS30L
IC2
(Note 3)
IC1
(Note 4)
LNBP21


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