SN74F163A

SYNCHRONOUS 4-BIT BINARY COUNTER

SDFS088A – MARCH 1987 – REVISED AUGUST 2001

7

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

VCC = 5 V,

TA = 25°C

MIN

MAX

UNIT

MIN

MAX

fclock

Clock frequency

0

100

0

90

MHz

CLK high or low (loading)

5

5

tw

Pulse duration

CLK (counting)

High

4

4

ns

CLK (counting)

Low

6

7

Data before CLK

↑

High or low

5

5

LOAD and CLR before CLK

↑

High

11

11.5

tsu

Setup time

LOAD and CLR before CLK

↑

Low

8.5

9.5

ns

ENP and ENT before CLK

↑

High

11

11.5

ENP and ENT before CLK

↑

Low

5

5

Data after CLK

↑

High or low

2

2

th

Hold time

LOAD and CLR after CLK

↑

High

2

2

ns

th

Hold time

LOAD and CLR after CLK

↑

Low

0

0

ns

ENP and ENT after CLK

↑

High or low

0

0

switching characteristics (see Note 4)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

CL = 50 PF,

RL = 500 Ω,

TA = 25°C

VCC = 4.5 V TO 5.5 V,

CL = 50 PF,

RL = 500 Ω,

TA = MIN TO MAX†

UNIT

MIN

TYP

MAX

MIN

MAX

fmax

100

120

90

MHz

tPLH

CLK (LOAD high)

Any Q

2.7

5.1

7.5

2.7

8.5

ns

tPHL

CLK (LOAD high)

Any Q

2.7

7.1

10

2.7

11

ns

tPLH

CLK (LOAD low)

Any Q

3.2

5.6

8.5

3.2

9.5

ns

tPHL

CLK (LOAD low)

Any Q

3.2

5.6

8.5

3.2

9.5

ns

tPLH

CLK

RCO

4.2

9.6

14

4.2

15

ns

tPHL

CLK

RCO

4.2

9.6

14

4.2

15

ns

tPLH

ENT

RCO

1.7

4.1

7.5

1.7

8.5

ns

tPHL

ENT

RCO

1.7

4.1

7.5

1.7

8.5

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

NOTE 4: Load circuits and waveforms are shown in Figure 1.