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MC100H601FNR2G Datasheet(PDF) 4 Page - ON Semiconductor |
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MC100H601FNR2G Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 6 page MC10H601, MC100H601 http://onsemi.com 4 Table 6. AC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = −5.2 V ± 5% (10H version); VEE = −4.2 V to −5.5 V (100H version) Symbol Parameter Condition 0°C 25°C 85°C Unit Min Max Min Max Min Max tPLH tPHL Propagation Delay to Output CL = 50 pF CL = 200 pF 1.7 3.4 4.8 9.6 1.7 3.4 4.8 9.6 1.7 3.4 4.8 9.6 ns ns tPLZ tPHZ Output Disable Time OEECL CL = 50 pF CL = 200 pF 3.7 5.4 6.5 13 3.7 5.4 6.5 13 3.7 5.4 6.5 13 ns ns tPLZ tPHZ OETTL CL = 50 pF CL = 200 pF 4.3 7.0 7.5 15 4.3 7.0 7.5 15 4.3 7.0 7.5 15 ns ns tPZL tPZH Output Enable Time OEECL CL = 50 pF CL = 200 pF 3.5 5.0 6.0 12 3.5 5.0 6.0 12 3.5 5.0 6.0 12 ns ns tPZL tPZH OETTL CL = 50 pF CL = 200 pF 4.2 6.0 7.0 14 4.2 6.0 7.0 14 4.2 6.0 7.0 14 ns ns tR tF Output Rise/Fall Time 1.0 V−2.0 V CL = 50 pF CL = 200 pF 1.2 3.0 1.2 3.0 1.2 3.0 ns ns NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. ORDERING INFORMATION Device Package Shipping† MC10H601FN PLCC−28 37 Units / Rail MC10H601FNG PLCC−28 (Pb−Free) 37 Units / Rail MC10H601FNR2 PLCC−28 500 / Tape & Reel MC10H601FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel MC100H601FN PLCC−28 37 Units / Rail MC100H601FNG PLCC−28 (Pb−Free) 37 Units / Rail MC100H601FNR2 PLCC−28 500 / Tape & Reel MC100H601FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices |
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