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CAT25080 Datasheet(Hoja de datos) 4 Page - Catalyst Semiconductor

No. de Pieza. CAT25080
Descripción  8-Kb and 16-Kb SPI Serial CMOS EEPROM
Descarga  17 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT25080, CAT25160
Doc. No. 1122 Rev. A
4
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PIN DESCRIPTION
SI:
The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
SO:
The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT25080/160.
CS
¯¯ :
The chip select input pin is used to enable/disable
the CAT25080/160. When CS
¯¯ is high, the SO output is
tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress). Every communication session between host
and CAT25080/160 must be preceded by a high to low
transition and concluded with a low to high transition of
the CS
¯¯ input.
WP
¯¯¯:
The write protect input pin will allow all write
operations to the device when held high. When WP
¯¯¯
pin is tied low and the WPEN bit in the Status
Register (refer to Status Register description, later in
this Data Sheet) is set to “1”, writing to the Status
Register is disabled.
HOLD
¯¯¯¯¯:
The HOLD
¯¯¯¯¯ input pin is used to pause trans–
mission between host and CAT25080/160, without
having to retransmit the entire sequence at a later
time. To pause, HOLD
¯¯¯¯¯ must be taken low and to
resume it must be taken back high, with the SCK
input low during both transitions. When not used for
pausing, the HOLD
¯¯¯¯¯ input should be tied to VCC,
either directly or through a resistor.
FUNCTIONAL DESCRIPTION
The CAT25080/160 devices support the Serial Periphe–
ral Interface (SPI) bus protocol, modes (0,0) and (1,1).
The device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
Reading data stored in the CAT25080/160 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT25080/160, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
After a high to low transition on the CS
¯¯ input pin, the
CAT25080/160 will accept any one of the six instruction
op-codes listed in Table 1 and will ignore all other
possible 8-bit combinations. The communication proto–
col follows the timing from Figure 1.
Table 1: Instruction Set
Instruction
Opcode
Operation
WREN
0000 0110 Enable Write Operations
WRDI
0000 0100 Disable Write Operations
RDSR
0000 0101 Read Status Register
WRSR
0000 0001 Write Status Register
READ
0000 0011 Read Data from Memory
WRITE
0000 0010 Write Data to Memory
Figure 1. Synchronous Data Timing
Note:
Dashed Line = mode (1, 1) - - - - - -
VALID IN
VIH
VIL
tCSS
VIH
VIL
VIH
VIL
VOH
VOL
HI-Z
tSU
tH
tWH
tWL
tV
tCS
tCSH
tHO
tDIS
HI-Z
CS
SCK
SI
SO
tRI
tFI




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