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CAT24C128 Datasheet(PDF) 4 Page - Catalyst Semiconductor

No. de Pieza. CAT24C128
Descripción  128-Kb I2C CMOS Serial EEPROM
Descarga  17 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
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CAT24C128 Datasheet(HTML) 4 Page - Catalyst Semiconductor

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Doc. No. 1103, Rev. G
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
The CAT24C128 incorporates Power-On Reset
(POR) circuitry which protects the device against
powering up in the wrong state.
The CAT24C128 will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device
address. When not driven, these pins are pulled LOW
WP: The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
The CAT24C128 supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C128
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver. Up to 8 devices may be
connected to the bus as determined by the device ad-
dress inputs A0, A1, and A2.
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices and must match the
state of the external address pins. The last bit, R/W
state of the external address pins. The last bit, R/
state of the external address pins. The last bit, R/ ,
specifies whether a Read (1) or Write (0) operation is
to be performed.
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge all address bytes and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle. As long as the Master acknowl-
edges the data, the Slave will continue transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by issuing a STOP
condition. Bus timing is illustrated in Figure 4.

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