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CAT24C128 Datasheet(PDF) 6 Page - Catalyst Semiconductor

No. de Pieza. CAT24C128
Descripción  128-Kb I2C CMOS Serial EEPROM
Descarga  17 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
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CAT24C128 Datasheet(HTML) 6 Page - Catalyst Semiconductor

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Doc. No. 1103, Rev. G
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Byte Write
Upon receiving a Slave address with the R/W
Upon receiving a Slave address with the R/
Upon receiving a Slave address with the R/
bit set
to ‘0’, the CAT24C128 will interpret the next two bytes
as address bytes These bytes are used to initialize the
internal address counter; the 2 most significant bits are
‘don’t care’, the next 8 point to one of 256 available pages
and the last 6 point to a location within a 64 byte page.
A byte following the address bytes will be interpreted as
data. The data will be loaded into the Page Write Buffer
and will eventually be written to memory at the address
specified by the 14 active address bits provided earlier.
The CAT24C128 will acknowledge the Slave address,
address bytes and data byte. The Master then starts
the internal Write cycle by issuing a STOP condition
(Figure 5). During the internal Write cycle (tWR), the SDA
output will be tri-stated and additional Read or Write
requests will be ignored (Figure 6).
Page Write
By continuing to load data into the Page Write Buffer
after the 1st data byte and before issuing the STOP
condition, up to 64 bytes can be written simultaneously
during one internal Write cycle (Figure 7). If more data
bytes are loaded than locations available to the end of
page, then loading will continue from the beginning of
page, i.e. the page address is latched and the address
count automatically increments to and then wraps-
around at the page boundary. Previously loaded data
can thus be overwritten by new data. What is eventually
written to memory reflects the latest Page Write Buffer
contents. Only data loaded within the most recent Page
Write sequence will be written to memory.
Acknowledge Polling
The ready/busy status of the CAT24C128 can be ascer-
tained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAT24C128 will not acknowledge the Slave address.
Hardware Write Protection
With the WP pin held HIGH, the entire memory
is protected against Write operations. If the WP
pin is left floating or is grounded, it has no im-
pact on the operation of the CAT24C128. The
state of the WP pin is strobed on the last falling
edge of SCL immediately preceding the first data byte
(Figure 8). If the WP pin is HIGH during the strobe in-
terval, the CAT24C128 will not acknowledge the data
byte and the Write request will be rejected.
Delivery State
The CAT24C128 is shipped erased, i.e., all bytes are

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