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CAT24C32 Datasheet(PDF) 4 Page - Catalyst Semiconductor

No. de Pieza. CAT24C32
Descripción  32-Kb I2C CMOS Serial EEPROM
Descarga  18 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT24C32 Datasheet(HTML) 4 Page - Catalyst Semiconductor

 
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CAT24C32
4
Doc. No. 1101, Rev. G
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POWER-ON RESET (POR)
Each CAT24C32 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into
Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level. This bi-directional POR
behavior protects the device against ‘brown-out’ failure
following a temporary loss of power.
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and
delivers output data. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device ad-
dress that must be matched by the corresponding Slave
address bits. The Address inputs are hard-wired HIGH
or LOW allowing for up to eight devices to be used
(cascaded) on the same bus. When left floating, these
pins are pulled LOW internally.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin
is pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C32 supports the Inter-Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a
Master device, which provides the clock and directs bus
traffic, and Slave devices which execute requests. The
CAT24C32 operates as a Slave device. Both Master
and Slave can transmit or receive, but only the Master
can assign those roles.
I2C BUS PROTOCOL
The 2-wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull-up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDAline.A‘0’is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics). During data transfer,
SDA must remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 1). The START consists of a
HIGH to LOW SDAtransition, while SCLis HIGH.Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW
to HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave address.
For the CAT24C32, the first four bits of the Slave address
are set to 1010 (Ah); the next three bits, A2, A1 and A0,
must match the logic state of the similarly named input
pins. The R/W
pins. The R/
pins. The R/
bit tells the Slave whether the Master
W
W
intends to read (1) or write (0) data (Figure 2).
Acknowledge
During the 9th clock cycle following every byte sent to
the bus, the transmitter releases the SDA line, allow-
ing the receiver to respond. The receiver then either
acknowledges (ACK) by pulling SDA LOW, or does not
acknowledge (NoACK) by letting SDAstay HIGH (Figure
3). Bus timing is illustrated in Figure 4.


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