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CAT24C64 Datasheet(PDF) 6 Page - Catalyst Semiconductor

No. de Pieza. CAT24C64
Descripción  64-Kb I2C CMOS Serial EEPROM
Descarga  18 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT24C64 Datasheet(HTML) 6 Page - Catalyst Semiconductor

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CAT24C64
6
Doc. No. 1102, Rev. H
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave ad-
dress with the R/W
dress with the R/
dress with the R/ bit set to ‘0’. The Master then sends
W
W
two address bytes and a data byte and concludes the
session by creating a STOP condition on the bus. The
Slave responds with ACK after every byte sent by the
Master (Figure 5). The STOP starts the internal Write
cycle, and while this operation is in progress (tWR), the
SDA output is tri-stated and the Slave does not acknowl-
edge the Master (Figure 6).
Page Write
The Byte Write operation can be expanded to Page
Write, by sending more than one data byte to the Slave
before issuing the STOP condition (Figure 7). Up to
32(1) distinct data bytes can be loaded into the internal
Page Write Buffer starting at the address provided by
the Master. The page address is latched, and as long
as the Master keeps sending data, the internal byte ad-
dress is incremented up to the end of page, where it then
wraps around (within the page). New data can therefore
replace data loaded earlier. Following the STOP, data
loaded during the Page Write session will be written to
memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress,
the Slave will not acknowledge the Master. This feature
enables the Master to immediately follow-up with a new
Read or Write request, rather than wait for the maximum
specified Write time (tWR) to elapse. Upon receiving a
NoACK response from the Slave, the Master simply re-
peats the request until the Slave responds with ACK.
Hardware Write Protection
WiththeWPpinheldHIGH,theentirememoryisprotected
against Write operations. If the WP pin is left floating or
is grounded, it has no impact on the Write operation. The
state of the WP pin is strobed on the last falling edge
of SCL immediately preceding the 1st data byte (Figure
8). If the WP pin is HIGH during the strobe interval, the
Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24C64 is shipped erased, i.e., all bytes are
FFh.
Note:
(1) CAT24C64 Rev. D (Not Recommended for New Designs) has
64-Byte Page Write Buffer.


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